This is similar to MCH in that it is used in various drivers. Add it to
the common header.
Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/x86/cpu/ivybridge/bd82x6x.c | 1 +
arch/x86/cpu/ivybridge/lpc.c | 6 ++++--
arch/x86/include/asm/arch-ivybridge/pch.h | 5 -----
arch/x86/include/asm/intel_regs.h | 4 ++++
4 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 9972b0a..55057e0 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -11,6 +11,7 @@
#include <pch.h>
#include <syscon.h>
#include <asm/cpu.h>
+#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/pci.h>
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9ab5ed3..26ffaa0 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -13,6 +13,7 @@
#include <rtc.h>
#include <pci.h>
#include <asm/acpi.h>
+#include <asm/intel_regs.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/ioapic.h>
@@ -420,7 +421,7 @@ static void enable_spi_prefetch(struct udevice *pch)
static void enable_port80_on_lpc(struct udevice *pch)
{
/* Enable port 80 POST on LPC */
- dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+ dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
clrbits_le32(RCB_REG(GCS), 4);
}
@@ -552,7 +553,8 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
{
/* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n");
- dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+ dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
+ RCB_BASE_ADDRESS | 1);
dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h
b/arch/x86/include/asm/arch-ivybridge/pch.h
index af3e8e7..628b517 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -211,11 +211,6 @@
#define SMBUS_TIMEOUT (10 * 1000 * 100)
-
-/* Root Complex Register Block */
-#define DEFAULT_RCBA 0xfed1c000
-#define RCB_REG(reg) (DEFAULT_RCBA + (reg))
-
#define PCH_RCBA_BASE 0xf0
#define VCH 0x0000 /* 32bit */
diff --git a/arch/x86/include/asm/intel_regs.h
b/arch/x86/include/asm/intel_regs.h
index 61e0ec2..0bc2fca 100644
--- a/arch/x86/include/asm/intel_regs.h
+++ b/arch/x86/include/asm/intel_regs.h
@@ -12,4 +12,8 @@
#define MCH_BASE_SIZE 0x8000
#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
+/* Access the Root Complex Register Block */
+#define RCB_BASE_ADDRESS 0xfed1c000
+#define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg))
+
#endif
--
2.7.0.rc3.207.g0ac5344
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