It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.
Signed-off-by: Simon Glass <s...@chromium.org>
---
doc/README.x86 | 9 +++++++++
scripts/coreboot.sed | 17 +++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 scripts/coreboot.sed
diff --git a/doc/README.x86 b/doc/README.x86
index d3fea5d..a3f45c7 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -812,6 +812,15 @@ PCIe root port's configuration registers will cause system
hang while it is
held in reset. For more details, check how they are implemented by the Intel
Galileo board support codes in board/intel/galileo/galileo.c.
+coreboot:
+
+See scripts/coreboot.sed which can assist with porting coreboot code into
+U-Boot drivers. It will not resolve all build errors, but will perform common
+transformations. Remember to add attribution to coreboot for new files added
+to U-Boot. This should go at the top of each file and list the coreboot
+filename where the code originated.
+
+
TODO List
---------
- Audio
diff --git a/scripts/coreboot.sed b/scripts/coreboot.sed
new file mode 100644
index 0000000..42e1f3a
--- /dev/null
+++ b/scripts/coreboot.sed
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Script to convert coreboot code to something similar to what U-Boot uses
+# sed -f coreboot.sed <coreboot_file.c>
+# Remember to add attribution to coreboot for new files added to U-Boot.
+s/REG_RES_WRITE32(\(.*\), \(.*\), \(.*\)),/writel(\3, base + \2);/
+s/REG_RES_POLL32(\(.*\), \(.*\), \(.*\), \(.*\), \(.*\)),/ret = poll32(base +
\2, \3, \4, \5);/
+s/REG_RES_OR32(\(.*\), \(.*\), \(.*\)),/setbits_le32(base + \2, \3);/
+s/REG_RES_RMW32(\(.*\), \(.*\), \(.*\), \(.*\)),/clrsetbits_le32(base + \2,
~\3, \4);/
+/REG_SCRIPT_END/d
+s/read32/readl/
+s/write32(\(.*\), \(.*\))/writel(\2, \1)/
+s/conf->/plat->/
+s/static const struct reg_script \(.*\)_script\[\] = {/static int \1(struct
udevice *dev)/
--
2.7.0.rc3.207.g0ac5344
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