On 09/11/2015 04:12 PM, Lukasz Majewski wrote:
[..]
> Please look into ELCE2014 slides from u-boot mini summit at Dusseldorf
> (slides are available at denx.de webpage).
>
> There was a presentation from Simon Glass regarding device model road
> map.
http://www.denx.de/wiki/U-Boot/MiniSummitELCE20
Hi Blibbet,
> Hi,
>
> First post on list.I'm mostly UEFI-centric, currently trying to learn
> u-boot...
>
> Is there any roadmap/plan for upcoming architectural changes to
> U-Boot?
Please look into ELCE2014 slides from u-boot mini summit at Dusseldorf
(slides are available at denx.de webpage)
From: Stephen Warren
Commit 6a132416359e "ci_udc: Update the ci_udc driver to support bulk
transfers" caused the value of "len" to change without updating subsquent
users of that variable in ci_ep_submit_next_request(). This caused the
code that detects when to emit ZLPs (Zero Length Packets) nev
Hi,
First post on list.I'm mostly UEFI-centric, currently trying to learn
u-boot...
Is there any roadmap/plan for upcoming architectural changes to U-Boot?
I recently saw the below comment on a Debian ARM list. I'm hoping u-boot
has something like that, but more detailed, for newbies like me to
u
Hi Alexey,
> Hi Marek, Lukasz,
>
> > On Wednesday, September 09, 2015 at 09:01:30 AM, Lukasz Majewski
> > wrote:
> > > Hi,
> > >
> > > > The commit: d9dbb97be0e4a550457aec5f11afefb446169c90
> > > > "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting
> > > > for end of dw mmc transfer
Hi Wenyou,
On 09/11/2015 10:01 AM, Yang, Wenyou wrote:
+
> >+void at91_enable_periph_generated_clk(u32 id) {
> >+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> >+ u32 regval;
> >+
> >+ if (id > AT91_PMC_PCR_PID_MASK)
> >+ return;
> >+
> >+ writel(id
Turns out what I have works once I turn on the hush parser...
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
--
View this message in context:
http://u-boot.10912.n7.nabble.com/Condition-in-bootcmd-to-run-bootz-else-bootm-tp228003p228030.html
Sent from the U-Boot mailing li
Hi Codrin,
On Wed, Sep 9, 2015 at 10:00 AM, Codrin Ciubotariu
wrote:
> The new command:
> ethsw [port ] [vlan ] fdb
> { [help] | show | flush | { add | del } }
>
> Can be used to add and delete FDB entries. Also, the command can be used
> to show entries from the FDB tables. When used wi
Hi Codrin,
On Wed, Sep 9, 2015 at 10:00 AM, Codrin Ciubotariu
wrote:
> The code that checks if a string has the format of a MAC address has been
> moved to a separate function called eth_validate_ethaddr_str().
>
> This has been done to allow other components (such as vsc9953 driver)
> to validat
Hi Bin,
On Fri, Sep 4, 2015 at 6:56 AM, Bin Meng wrote:
> In get_phy_device_by_mask(), when no phy is found, we should not
> create any phy device.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx.de
htt
Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.
Signed-off-by: Vikas Manocha
---
Changes in v6: none
Changes in v5: none
Changes in v4: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts
This patch is to separate the base trigger from the read/write transfer start
addresses.
Base trigger register address (0x1c register) corresponds to the address which
should be put on AHB bus to handle indirect transfer triggered before.
To handle indirect transfer we need to issue addresses fro
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha
---
Changes in v6: none
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra
plat->ahbbase renamed to plat->flashbase for better clarity.
Signed-off-by: Vikas Manocha
---
Changes in v6: none
Changes in v5: none
Changes in v4: new
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
drivers/spi/cadence_qspi_apb.c |4 ++--
3 fil
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha
---
Changes in v6: None
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: added commit message & removed extra bracket.
Changes in v2: Rebas
This patchset:
- fixes trigger base & transfer start address register programming. This fix
superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger
address setting".
- adds support to get fifo width from device tree
Changes in v6:
- fixed binding for trigger-address.
Change
On Fri, 2015-09-11 at 08:23 +0200, Stefan Roese wrote:
> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
> be used by boards equipped with a NAND chip that requires 4-bit ECC
> strength.
> The SPEAr600 HW ECC only supports 1-bit ECC strength.
>
> To enable SW BCH4, you n
On 09/09/2015 11:07 AM, Simon Glass wrote:
> +Stephen
>
> Hi Stefan,
>
> On Thursday, 3 September 2015, Stefan Roese wrote:
>>
>> The current "simple" address translation simple_bus_translate() is not
>> working on some platforms (e.g. MVEBU). As here more complex "ranges"
>> properties are used
Hi Stefan,
On 09/04/2015 06:44 PM, Stefan Roese wrote:
Unfortunately u-boot now hangs if I try to load an image from the
SD-Card:
e.g. if I run the following command u-boot hangs:
ext4load mmc 0:2 0x200 /boot/kernel.bin
I don't see why exactly it crashes, it seems for me that it's always
Hi Stefan,
On 09/11/2015 04:24 PM, Stefan Roese wrote:
Hi Stefan,
On 11.09.2015 15:50, Stefan Eichenberger wrote:
On 09/04/2015 06:44 PM, Stefan Roese wrote:
Unfortunately u-boot now hangs if I try to load an image from the
SD-Card:
e.g. if I run the following command u-boot hangs:
ext4load
From: Shaohui Xie
commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of
T4240QDS board", T4160 also needs this fix.
Signed-off-by: Shaohui Xie
---
drivers/mmc/fsl_esdhc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc
Hi Marek, Lukasz,
> On Wednesday, September 09, 2015 at 09:01:30 AM, Lukasz Majewski wrote:
> > Hi,
> >
> > > The commit: d9dbb97be0e4a550457aec5f11afefb446169c90
> > > "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for
> > > end of dw mmc transfer.
> > >
> > > For some workload
Hi Marek,
On Fri, 2015-09-11 at 13:49 +0200, Marek Vasut wrote:
> On Friday, September 11, 2015 at 09:59:32 AM, Alexey Brodkin wrote:
> > Hi Marek,
>
> Hi!
> btw Is your mailer totally broken by any chance ?
Hm, I'm not sure what happened but as I may see here
https://patchwork.ozlabs.org/patch
On 09/10/2015 03:26 PM, Tom Rini wrote:
> On Thu, Sep 10, 2015 at 10:22:35AM -0700, Stephen Warren wrote:
>> On 07/28/2015 08:55 PM, Stephen Warren wrote:
>>> The FAT code contains a special case to parse the root
>>> directory. This is needed since the root directory
>>> location/layout on disk is
Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/spl.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c
index 75d2989..2267b13 100644
--- a/arch/arm/ma
Masahiro Yamada (5):
ARM: uniphier: remove unused header file
ARM: uniphier: remove useless wrapper functions
ARM: uniphier: refactor LED function
ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file
ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARD
arch/arm/mach-un
From: Fabio Estevam
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Signed-off-by: Fabio Estevam
---
board/udoo/udoo.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --gi
From: Fabio Estevam
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Markus Niebel
Signed-off-by: Fabio Estevam
---
board/tqc/tqma6/tqma6_mba6.c | 20 +++-
1 file changed, 11 insertion
This has been unused since commit f4e190e317b8 ("ARM: uniphier:
enable SPL_OF_CONTROL").
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/include/mach/platdevice.h | 24
1 file changed, 24 deletions(-)
delete mode 100644 arch/arm/mach-uniphier/include/mach/pla
The macro, led_write(), is now only used in C sources. There is no
more reason to keep the tricky assembly macro. Replace it with a
new C function led_puts().
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/board_common.c | 11 +--
arch/arm/mach-uniphier/board_early_init_f.c
The wrapper functions, uniphier_board_*, are just making function
calls complex. Remove them.
Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/board_early_init_r.c | 5 +
It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros. Also, rename the C file.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/Makefile | 2 +-
.../{support_card.c => micro-support-card.c} |
On 9/10/2015 8:53 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> We should not return 0 on failure, so return a negative error code
> instead.
>
> Also centralize the error path so that is easier to follow.
>
> Cc: Troy Kisky
> Signed-off-by: Fabio Estevam
> ---
> board/boundary/nitroge
Hi, I'd like to set a condition in bootcmd to run uImage from flash if it
can't find zImage on the filesystem.
Here is our zImage bootcmd...
mmc dev 0; ext2load mmc 0:1 ${loadaddr} /opt/common/var/zImage; ext2load mmc
0:1 0x7100 /opt/common/var/dtb; bootz ${loadaddr} - 0x7100
Here is our
Hi Tom,
Here is another sunxi pull-req for v2015.10, highlights:
-Add support for 5 new boards
-Misc fixes
The following changes since commit efde6a579fe3c172d214fb3047b02c827779738a:
Prepare v2015.10-rc3 (2015-09-07 08:56:35 -0400)
are available in the git repository at:
http://git.denx
Hi Stefan,
On 11.09.2015 15:50, Stefan Eichenberger wrote:
On 09/04/2015 06:44 PM, Stefan Roese wrote:
Unfortunately u-boot now hangs if I try to load an image from the
SD-Card:
e.g. if I run the following command u-boot hangs:
ext4load mmc 0:2 0x200 /boot/kernel.bin
I don't see why exact
On Fri, Sep 11, 2015 at 09:45:22AM +0200, Andreas Bießmann wrote:
> Hi Tom,
>
> hopefully the last pull request for 2015.10 from atmel side. It finally
> contains a fix for two siemens boards (axm, taurus) for SPL size check, a DFU
> series for armv5 at91 devices acked by Łukasz Majewski and some
On Friday, September 11, 2015 at 09:59:32 AM, Alexey Brodkin wrote:
> Hi Marek,
Hi!
> On Mon, 2015-07-27 at 22:39 +-0200, Marek Vasut wrote:
> +AD4- Endless timeouts are bad, since if we get stuck in one, we have no
> +AD4- way out. Zap this one by implementing proper timeout.
> +AD4-
> +AD4- Sig
From: Shaohui Xie
phy_shutdown should be wrapped by CONFIG_PHYLIB.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
drivers/net/fm/eth.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index cd05dbc..67c96a2
From: Shaohui Xie
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
arch/powerpc/include/asm/fsl_dtsec.h| 231 --
Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards. It has been painful to maintain
both. Having one of them is enough.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
---
Changes
To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
arch/arm/mach-uniphier/include/mach/sg-regs.h| 40 +++
arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug
Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB
(spl/u-boot-spl.dtb).
The "soc" node (this is simple-bus node) also needs the property
to bind the pinctrl node located under it.
I am collecting this U-Boot specific hack to the bottom of board
DTS rather than inserting "u-boot,dm-pre
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
0x - 0x0fff
0x4000 - 0x4fff
are both mapped to the external bus (also called system bus),
so either was OK.
In the newest two SoCs, the former (0x - 0x0fff) is
assigned for the serial NOR interfa
Device tree specifies the available memory ranges in its "/memory"
node. Use it to simplify the CONFIG defines.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
arch/arm/mach-uniphier/board_common.c | 12 -
arch/arm/mach-uniphier/dram_init.c| 51 +
Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add input-enable settings
- Sync pin-mux table with Linux pinctrl driver
drivers/pinctrl/uniphier/Kconfig| 6 ++
drivers/pinctrl/uniphier/Makefile
This command will be used in the next commit to calculate
base-offseted addresses.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/ph1_ld4_defconfig | 1 -
configs/ph1_pro4_defconfig | 1 -
configs/ph1_sld3_defconfig | 1 -
configs/ph1_sld8_defconfig | 1 -
4 files changed, 4 d
The core support for the pinctrl drivers for all the UniPhier SoCs.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
---
Changes in v2:
- add comments to structures
- re-design to maximize code re-use of Linux pinctrl drivers
- implement input enabling
drivers/pinctrl/Kconfig
These input enable settings are handled by the pinctrl drivers.
Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Newly added
arch/arm/mach-uniph
Now, UniPhier SoCs are ready to enable pinctrl drivers.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/ph1_ld4_defconfig | 2 ++
configs/ph1_pro4_defconfig | 2 ++
configs/ph1_sld8_defconfig | 2 ++
3 files changed, 6 insertions(+)
diff --git a/configs/ph1_ld4_defconfig b/con
As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
---
Changes in v2: None
arch/arm/mach-uniphier/ph1-ld4/Make
Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add input-enable settings
- Sync pin-mux table with Linux pinctrl driver
drivers/pinctrl/uniphier/Kconfig| 6 ++
drivers/pinctrl/uniphier/Makefile
Masahiro Yamada (18):
pinctrl: uniphier: add UniPhier pinctrl core support
pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver
pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver
pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver
pinctrl: uniphier: add UniPhier PH1-Pro5 pin
Add pin configuration and pinmux support for UniPhier ProXstream2
SoC.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add input-enable settings
- Sync pin-mux table with Linux pinctrl driver
drivers/pinctrl/uniphier/Kconfig | 6 ++
drivers/pinctrl/uniphier/Makefile
In the next commit, I will add "u-boot,dm-pre-reloc" to the "soc"
(simple-bus) nodes in UniPhier device trees. But, before that,
CONFIG_SYS_MALLOC_F_LEN must be increased.
Adding "u-boot,dm-pre-reloc" to a simple-bus node causes it to bind
all of its child nodes. (See simple_bus_post_bind() func
Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add input-enable settings
- Sync pin-mux table with Linux pinctrl driver
drivers/pinctrl/uniphier/Kconfig| 6 ++
drivers/pinctrl/uniphier/Makefile
In UniPhier device trees, pinctrl device nodes are located under the
simple-bus (AMBA).
This is needed to bind pinctrl devices in SPL.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/ph1_ld4_defconfig | 1 +
configs/ph1_pro4_defconfig | 1 +
configs/ph1_sld8_defconfig | 1 +
3
Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add input-enable settings
- Sync pin-mux table with Linux pinctrl driver
drivers/pinctrl/uniphier/Kconfig | 6 ++
drivers/pinctrl/uniphier/Makefile |
Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add input-enable settings
- Sync pin-mux table with Linux pinctrl driver
drivers/pinctrl/uniphier/Kconfig| 6 ++
drivers/pinctrl/uniphier/Makefile
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043ardb/cpld.c | 17 +
board/freescale/ls1043ardb/cpld.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/board/freescale/ls1043ardb/cpld.c
b/board/freescale/ls1043ardb/cpld.c
index 5acb97d..faa0de8 100644
--- a/board/frees
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043ardb/ls1043ardb.c | 8 +++
board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 ++
configs/ls1043ardb_sdcard_defconfig | 4
include/configs/ls1043a_common.h | 30
i
From: Yangbo Lu
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/fsl-lsch2/cpu.c | 10 ++
arch/arm/cpu/armv8/fsl-lsch2/fdt.c | 6 ++
arch/arm/cpu/armv8/fsl-lsch2/speed.c | 18 +-
drivers/m
From: Mingkai Hu
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/Makefile |
From: Shaohui Xie
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/fsl-lsch2/cpu.c | 19 +
arch/arm/cpu/armv8/fsl-lsch2/fdt.c | 7 ++
arch/arm/cpu/armv8/fsl-lsch2/speed.c| 23 ++
board
From: Mingkai Hu
LS1043ARDB Specification:
-
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit but)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI memory
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G po
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043ardb/cpld.c | 18 ++
board/freescale/ls1043ardb/cpld.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/board/freescale/ls1043ardb/cpld.c
b/board/freescale/ls1043ardb/cpld.c
index 3f1101e..5acb97d 100644
--- a/board/free
Signed-off-by: Gong Qianyu
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
---
arch/arm/Kconfig | 1 +
arch/arm/cpu/armv8/fsl-lsch2/Makefile | 1 +
arch/arm/cpu/armv8/fsl-lsch2/spl.c | 91
This patch fixes such compile warnings:
drivers/net/fm/eth.c: In function 'fm_eth_recv':
drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
drivers/net/fm/fm.c: In function 'fm_muram_alloc':
From: Shaohui Xie
MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
From: Shaohui Xie
QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: Shaohui Xie
Signed-off-by: Mi
From: Shaohui Xie
Remove the redundant byte swap of the ucode before uploading to IRAM.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
drivers/net/fm/eth.c | 69 +++-
drivers/net
On Wednesday 09 September 2015 11:38 PM, Simon Glass wrote:
> Hi,
>
> On Monday, 7 September 2015, Mugunthan V N wrote:
>>
>> On Friday 07 August 2015 03:01 AM, Stephen Warren wrote:
>>> From: Stephen Warren
>>>
>>> fdtdec_get_addr_size() hard-codes the number of cells used to represent
>>> an a
Hi Simon,
On Fri, Sep 11, 2015 at 4:41 AM, Simon Glass wrote:
> Hi Bin,
>
> On 9 September 2015 at 21:58, Simon Glass wrote:
>> On 3 September 2015 at 06:37, Bin Meng wrote:
>>> Introduce device_is_on_pci_bus() which can be utilized by driver
>>> to test if a device is on a PCI bus.
>>>
>>> Sig
The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.
Signed-off-by: Bin Meng
---
Changes in v5:
- Wrap PCI device support with CONFIG_DM_PCI
Changes in v3:
- Change to use dm_pci_read_config32()
Changes in v2:
- Change
Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v5: None
Changes in v3: None
Changes in v2: None
arch/x86/cpu/quark/quark.c | 19 ---
configs/galileo_defconfig | 2 +-
2 files chang
This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v5: None
Changes in v3: None
Changes i
Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.
Signed-off-by: Bin Meng
---
Changes in v5:
- Move the inline API from include/pci.h to include/dm/device.h to
resolve the cyclic dependency
Changes in v3: None
Changes in v2:
- New patch to
Dear Tom,
In message <20150908001955.GF26226@bill-the-cat> you wrote:
>
> I've pushed v2015.10-rc3 out to the repository and tarballs should exist
> soon.
Tarballs are inplace, both on FTP [1] and ACD [2].
[1] ftp://ftp.denx.de/pub/u-boot/
[2]
https://www.amazon.com/clouddrive/share/MjxAmOsCwX
Hi!
Am 10.09.2015 um 20:36 schrieb Hans de Goede:
Hi,
I would prefer to have this like this:
"bootcmd_fel=" \
"if test -n ${fel_booted} && test -n ${fel_data_addr}; then " \
"echo '(FEL boot)';" \
"source ${fel_data_addr}; " \
"fi\0"
Sure, we coul
Hi Hans!
Am 10.09.2015 um 20:34 schrieb Hans de Goede:
What if the user interrupts auto-boot with a fel provided boot.scr
and then does "saveenv" ?
Then we end up with a fel_data_addr and fel_data_size permanently
in the env.
At a minimum this function must always do:
setenv("fel_data_addr",
On Thu 2015-09-10 00:01:42, Chin Liang See wrote:
> Ensure the intended SCLK frequency not exceeding the maximum
> frequency. If that happen, SCLK will set to maximum frequency.
-> that happens, SCLK will be set to the maximum frequency.
Acked-by: Pavel Machek
--
(english) http://www.livejourn
Hello Hans!
Thanks for looking into this.
Am 10.09.2015 um 20:29 schrieb Hans de Goede:
I believe these 2 should be renamed to:
uint32_t fel_boot_script_address;
uint32_t fel_boot_script_size;
To properly reflect what they are (they are not some abstract
data, they are specifically a
Hi,
On 09/11/2015 02:43 AM, Simon Glass wrote:
Hi Marek,
On 10 September 2015 at 04:40, Marek Vasut wrote:
On Thursday, September 10, 2015 at 04:45:53 AM, Simon Glass wrote:
Hi Marek,
On 8 September 2015 at 12:33, Marek Vasut wrote:
On Tuesday, September 08, 2015 at 07:15:11 PM, Simon Gla
Hi Marek,
On Mon, 2015-07-27 at 22:39 +0200, Marek Vasut wrote:
> Endless timeouts are bad, since if we get stuck in one, we have no
> way out. Zap this one by implementing proper timeout.
>
> Signed-off-by: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Pantelis Antoniou
> Cc: Tom Rini
> ---
> drivers
Hi Tom,
hopefully the last pull request for 2015.10 from atmel side. It finally
contains a fix for two siemens boards (axm, taurus) for SPL size check, a DFU
series for armv5 at91 devices acked by Łukasz Majewski and some trivial fixes.
The following changes since commit f0dc73c090317c7d0660443bc
Hi Simon,
On 11.09.2015 02:42, Simon Glass wrote:
On Thursday, 3 September 2015, Stefan Roese wrote:
The current "simple" address translation simple_bus_translate() is not
working on some platforms (e.g. MVEBU). As here more complex "ranges"
properties are used in many nodes (multiple tuples
Hi Scott,
On 11.09.2015 00:31, Scott Wood wrote:
On Wed, 2015-09-02 at 14:29 +0200, Stefan Roese wrote:
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength.
The SPEAr600 HW ECC only supports 1-bit
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your config header:
And use the command "nan
From: Fabio Estevam
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Christian Gmeiner
Signed-off-by: Fabio Estevam
---
board/bachmann/ot1200/ot1200.c | 20
1 file changed, 12 ins
On Fri, Sep 4, 2015 at 9:53 AM, Bin Meng wrote:
> Currently there is no API to uninitialize mdio. Add two APIs for this.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Thu, Sep 10, 2015 at 03:50:36PM -0700, Simon Glass wrote:
> Hi Tom,
>
> Here are a few more driver model PCI fixes, the tftp revert and some
> driver model conversions for x86, as well as a few other minor fixes.
> There are a few more patches in flight but I could not apply them due
> to prob
From: Fabio Estevam
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Troy Kisky
Signed-off-by: Fabio Estevam
---
board/boundary/nitrogen6x/nitrogen6x.c | 19 +++
1 file changed, 11 ins
Hi Bo Shen,
Thank you for your review.
> -Original Message-
> From: Bo Shen [mailto:voice.s...@gmail.com]
> Sent: 2015年9月10日 6:51
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH] arm: at91: clock: Add the generated clock
> support
>
> Hi Wenyou,
>
> On 09/09/2015
Hi Joe,
On Fri, Sep 11, 2015 at 6:30 AM, Joe Hershberger
wrote:
> Hi Bin,
>
> On Fri, Sep 4, 2015 at 9:53 AM, Bin Meng wrote:
>> Currently there is no API to uninitialize mdio. Add two APIs for this.
>
> Is this causing some failure in the short term? The plan is to move
> eth phy support to dri
Dear Heiko Schocher,
Heiko Schocher writes:
>add U-Boot specific changes to the at91_udc linux driver,
>so it works with U-Boot.
>
>Signed-off-by: Heiko Schocher
>---
>
>Changes in v5:
>- add comment from Andreas Biessmann:
> remove BIT() usage in driver, also removed patch
> which introduced
Dear Daniel Gorsulowski,
Daniel Gorsulowski writes:
>Signed-off-by: Daniel Gorsulowski
>Reviewed-by: Simon Glass
>[fix corrupt line wraps in patch]
>Signed-off-by: Andreas Bießmann
>---
> include/configs/meesc.h | 2 ++
> 1 file changed, 2 insertions(+)
applied to u-boot-atmel/master, thanks
Dear Heiko Schocher,
Heiko Schocher writes:
>[root@pollux dfu-util]# ./src/dfu-util -l
>dfu-util 0.8
>
>Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
>Copyright 2010-2014 Tormod Volden and Stefan Schmidt
>This program is Free Software and has ABSOLUTELY NO WARRANTY
>Please re
Dear Josh Wu,
Josh Wu writes:
>From: Bo Shen
>
>Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE
>into the console and hitting enter afterwards, causes a hang in the
>system because CONFIG_SYS_PBSIZE is not capable of storing the extra
>characters of the error message:
>"Un
Dear Heiko Schocher,
Heiko Schocher writes:
>port at91_udc driver from linux:
>
>original commit Message:
>commit c94e289f195e0e13cf34d27f9338d28221a85751
>Author: Arnd Bergmann
>Date: Sat Apr 11 00:14:21 2015 +0200
>
>usb: gadget: remove incorrect __init/__exit annotations
>
>A recent
Dear Heiko Schocher,
Heiko Schocher writes:
>taurus changes:
>- rename at91_spl_board_init to spl_board_init
> fixes problems with recovery button and nand erase sector 0
>- adapt CONFIG_SPL_MAX_SIZE and CONFIG_SPL_BSS_MAX_SIZE
>- add CONFIG_AT91_HW_WDT_TIMEOUT 15
>- CONFIG_SF_DEFAULT_MODE SPI_M
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