There are still a few pending patches that I'm waiting to hear back about,
and you or Kumar have applied most of the others, but this one has been
cleaned up and applied to my tree.
The following changes since commit a47a12becf66f02a56da91c161e2edb625e9f20c:
Stefan Roese (1):
Move arch/p
On Wed, Apr 7, 2010 at 10:31 AM, Kumar Gala wrote:
> From: Jerry Huang
>
> Multiple block read support to improve performance (time it takes) to read
> larger amounts of data.
>
> Signed-off-by: Jerry Huang
> Signed-off-by: Roy Zang
How well has this been tested? I recall that there was some
On 24/04/2010, at 11:42 AM, Wolfgang Denk wrote:
> In message you wrote:
>>
>> OK, so reducing the number of reads from registers and writes to RAM
>> should improve performance. To you knowledge, would enabling the
>> cache for davinci da850 break anything in U-Boot?
>
> No, except that it shou
On Fri, Apr 23, 2010 at 8:29 PM, Marek Vasut wrote:
> Dne So 24. dubna 2010 03:13:07 Andy Fleming napsal(a):
>> On Sun, Apr 4, 2010 at 7:32 PM, Marek Vasut wrote:
>> > In case the delays were set to 1, the MMC card on PXA27X boards (and
>> > PXA3xx boards) didn't initialize on first try. Incr
Dne So 24. dubna 2010 03:22:08 Andy Fleming napsal(a):
> On Fri, Mar 26, 2010 at 12:57 AM, Marek Vasut wrote:
> > ---
> > drivers/mmc/pxa_mmc.c | 13 -
> > 1 files changed, 8 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c
> > index
Dne So 24. dubna 2010 03:13:07 Andy Fleming napsal(a):
> On Sun, Apr 4, 2010 at 7:32 PM, Marek Vasut wrote:
> > In case the delays were set to 1, the MMC card on PXA27X boards (and
> > PXA3xx boards) didn't initialize on first try. Increasing the delays and
> > leaving just those for PXA25x an
On Fri, Apr 23, 2010 at 6:21 PM, Albin Tonnerre
wrote:
> On Fri, 23 Apr 2010 16:58 -0500, Andy Fleming wrote :
>> On Thu, Apr 22, 2010 at 7:51 PM, Rob Emanuele wrote:
>> > Hi Henry & U-Boot Community,
>> >
>> > I've been experiencing the same errors and frustration you have.
>> >
>> > So I've bee
On Fri, Mar 26, 2010 at 12:57 AM, Marek Vasut wrote:
> ---
> drivers/mmc/pxa_mmc.c | 13 -
> 1 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c
> index 8225235..18d5df9 100644
> --- a/drivers/mmc/pxa_mmc.c
> +++ b/drivers/
On Sun, Apr 4, 2010 at 7:32 PM, Marek Vasut wrote:
> In case the delays were set to 1, the MMC card on PXA27X boards (and
> PXA3xx
> boards) didn't initialize on first try. Increasing the delays and leaving just
> those for PXA25x and 26x (that is 20) fixes this problem.
In general, I o
Dear Delio Brignoli,
In message you wrote:
>
> OK, so reducing the number of reads from registers and writes to RAM
> should improve performance. To you knowledge, would enabling the
> cache for davinci da850 break anything in U-Boot?
No, except that it should be done consistently for all ARM p
Hello Wolfgang,
On 24/04/2010, at 10:29 AM, Wolfgang Denk wrote:
> please mind the NetiQuette and restrict your line length to some 70
> charatcers or so. Thanks.
Will do, thanks.
> Everything is slow as caches are not enabled.
OK, so reducing the number of reads from registers and writes to R
On Fri, 23 Apr 2010 16:58 -0500, Andy Fleming wrote :
> On Thu, Apr 22, 2010 at 7:51 PM, Rob Emanuele wrote:
> > Hi Henry & U-Boot Community,
> >
> > I've been experiencing the same errors and frustration you have.
> >
> > So I've been looking at this code and these patch sets for a day or
> > two
Dear Delio Brignoli,
please mind the NetiQuette and restrict your line length to some 70
charatcers or so. Thanks.
In message <4d573595-069a-4490-af2d-38ed3aad7...@audioscience.com> you wrote:
>
> I am working on reducing boot time on an L138 EVM and SPI flash transfer
> speed is currently the
Dear Wolfgang Wegner,
In message <20100423205938.gu20...@leila.ping.de> you wrote:
> This patch adds bootcount for Freescale MCF5445x. Two registers of
> eDMA transfer control descriptors (TCD[1]) are used because these
> are unused by linux kernel (freescale LTIB linux-2.6.25) and were
> tested t
Hello Sekhar,
I am working on reducing boot time on an L138 EVM and SPI flash transfer speed
is currently the worst offender. U-Boot transfers from the SPI flash at
0.6Mbytes/s, this a lot slower than I would expect for a 50MHz SPI clock. Using
a scope we found that the chip select is active th
On Thu, Apr 22, 2010 at 7:51 PM, Rob Emanuele wrote:
> Hi Henry & U-Boot Community,
>
> I've been experiencing the same errors and frustration you have.
>
> So I've been looking at this code and these patch sets for a day or
> two now. I've done that in conjunction with reading the SD card spec:
This patch adds bootcount for Freescale MCF5445x. Two registers of
eDMA transfer control descriptors (TCD[1]) are used because these
are unused by linux kernel (freescale LTIB linux-2.6.25) and were
tested to keep their contents across resets.
TCD[1] is currently unused by the linux drivers, so usi
Dear Wolfgang Denk,
On Fri, Apr 23, 2010 at 10:47:53PM +0200, Wolfgang Denk wrote:
[...]
> Um... I think this was a misunderstanding. This comment here is lost
> in the git repository.
only half misunderstanding and half too late for me today... Sorry!
Best regards,
Wolfgang
___
Dear Wolfgang Wegner,
In message <20100423202642.gt20...@leila.ping.de> you wrote:
> This patch adds bootcount for Freescale MCF5445x. Two registers of
> eDMA transfer control descriptors (TCD[1]) are used because these
> are unused by linux kernel (freescale LTIB linux-2.6.25) and were
> tested t
This patch adds bootcount for Freescale MCF5445x. Two registers of
eDMA transfer control descriptors (TCD[1]) are used because these
are unused by linux kernel (freescale LTIB linux-2.6.25) and were
tested to keep their contents across resets.
Signed-off-by: Wolfgang Wegner
---
I implemented and
Hello Michael,
On Fri, 23 Apr 2010 22:06:09 +0300
Michael Zaidman wrote:
> The patches implement first 2 steps of POST framework cleanup
> suggested by Wolfgang Denk in the
> http://lists.denx.de/pipermail/u-boot/2010-April/070400.html
Are you working on a patch addressing the 3rd step?
I need
Hello Guys,
I would like to know what are the possible chances that u-boot/ubl crashes?.
I am looking for some theory/scenario that I can possibly connect/apply the
scenario to what happened to my device based on dm6446.
The device has been running for a year now and for some reason it never come
Dear Wolfgang Wegner,
In message <20100423194341.gs20...@leila.ping.de> you wrote:
>
> > > + * We use transfer descriptor registers as a persistent storage
> > > + * across resets. This was tested on a MCF54455.
> > > + * Neither U-Boot nor the stock LTIB kernel seem to use
> > > + * TCD[1], so i
Dear Wolfgang Denk,
On Fri, Apr 23, 2010 at 09:25:35PM +0200, Wolfgang Denk wrote:
> Dear Wolfgang Wegner,
>
> In message <1272026324-18566-1-git-send-email-w.weg...@astro-kom.de> you
> wrote:
> > This patch adds bootcount for Freescale MCF5445x. Two registers of
> > eDMA transfer control descri
Dear Mike Frysinger,
In message <201004231533.58136.vap...@gentoo.org> you wrote:
>
> it. i could just as easily say "i'd rather the code didnt assume powerpc
> everywhere", but it isnt like that gets us from point a to point b.
I would have preferred an architecture neutral implementation as w
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On Friday 23 April 2010 15:30:09 Wolfgang Denk wrote:
> Mike Frysinger wrote:
> > because the post/ dir has historically been ppc-only (literally sprinkled
> > with code that would not compile for any other arch), we were filtering
> > post/ out in the top level Makefile for Blackfin targets.
> > i
Dear Mike Frysinger,
In message <201004231137.16732.vap...@gentoo.org> you wrote:
>
> because the post/ dir has historically been ppc-only (literally sprinkled
> with
> code that would not compile for any other arch), we were filtering post/ out
> in the top level Makefile for Blackfin targets.
Dear Wolfgang Wegner,
In message <1272026324-18566-1-git-send-email-w.weg...@astro-kom.de> you wrote:
> This patch adds bootcount for Freescale MCF5445x. Two registers of
> eDMA transfer control descriptors (TCD[1]) are used because these
> are unused by linux kernel (freescale LTIB linux-2.6.25)
1) post/post.c instead of arch/blackfin/lib/post.c
2) Alternative post_list support.
Suggested-by: Wolfgang Denk
Signed-off-by: Michael Zaidman
---
arch/blackfin/lib/Makefile|2 +-
arch/blackfin/lib/board.c |1 -
arch/blackfin/lib/post.c | 421 -
Signed-off-by: Michael Zaidman
Suggested-by: Wolfgang Denk
---
arch/powerpc/cpu/mpc8260/commproc.c | 24
arch/powerpc/cpu/mpc8260/cpu.c | 24
arch/powerpc/cpu/mpc8xx/commproc.c | 26 --
arch/powerpc/cpu/mpc8xx/
The patches implement first 2 steps of POST framework cleanup
suggested by Wolfgang Denk in the
http://lists.denx.de/pipermail/u-boot/2010-April/070400.html
Michael Zaidman (2):
The bootcount_{store|load} moved to arch specific generic locations.
Blackfin: POST: revive, sync to main stream, c
Signed-off-by: Magnus Lilja
---
include/configs/imx31_litekit.h | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 6131008..d58ca8a 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/co
Add sec3.1 h/w geometry for fdt node fixups.
Also, technically, whilst SEC v3.3 h/w honours the tls_ssl_stream descriptor
type, it lacks the ARC4 algorithm execution unit required to be able
to execute anything meaningful with it. Change the node to agree with
the documentation that declares that
23.04.2010 19:11, Mike Frysinger wrote:
for future reference, you shouldnt put "patch" in the subject name ... i'm not
referring to the leading [PATCH], but the trailing "patch".
ok, thanx
also, i'm not sure if you're using `git send-email` because the trail of your
patch is missing the "---"
On Friday 23 April 2010 12:48:55 Valentin Yakovenkov wrote:
> I don't use git at all. We have mercurial "master repo" which is pulled
> from local "SVN synced repo" which is synchronized via svn with
> blackfin.uclinux.org.
b.u.o offers git as well if that makes things easier to sync:
http://black
On Friday 23 April 2010 12:31:21 Michael Zaidman wrote:
> Will you fix the CONFIG_{MMC,SPI_MMC} in the bf537-stamp.h header by
> yourself or you want me to do it it this patch set?
i'll take care of it
-mike
signature.asc
Description: This is a digitally signed message part.
On Fri, Apr 23, 2010 at 6:37 PM, Mike Frysinger wrote:
> On Friday 23 April 2010 11:21:28 Michael Zaidman wrote:
>> BTW, looking on the blackfin POST implementation I wonder if it was
>> used recently. Enabling POST on the bf537-stamp board caused the
>> post_list array of post/tests.c to be linke
On Fri, Apr 23, 2010 at 11:34:53AM -0400, Mike Frysinger wrote:
[...]
> > the problem exists in the (coldfire) SPI driver, not in the MMC/SD code.
>
> sorry, i thought you were proposing to fix it in the SPI/MMC driver
no, as far as I can see it is always set to 0xFF there if set explicitly,
i.e.
This patch adds CONFIG_SPI_IDLE_VAL to cf_spi.c
The default setting is 0x0 to behave same as current version, in case
CONFIG_SPI_MMC is set, the value is set to 0x (all ones). In either
case, the value can be overwritten by board configuration.
Signed-off-by: Wolfgang Wegner
---
drivers/spi/
On Fri, Apr 23, 2010 at 05:18:29PM +0200, Wolfgang Wegner wrote:
> (Only pitfall is that the current 0x0 is used for 8- as well as 16-bit
> transfers...)
forget about that, the register is alway written as 16 bits.
Regards,
Wolfgang
___
U-Boot mailing
On Friday 23 April 2010 11:21:28 Michael Zaidman wrote:
> BTW, looking on the blackfin POST implementation I wonder if it was
> used recently. Enabling POST on the bf537-stamp board caused the
> post_list array of post/tests.c to be linked instead of
> arch/blackfin/cpu/lib/tests.c as was expected.
On Friday 23 April 2010 11:18:29 Wolfgang Wegner wrote:
> On Fri, Apr 23, 2010 at 11:08:10AM -0400, Mike Frysinger wrote:
> > On Friday 23 April 2010 04:43:07 Wolfgang Wegner wrote:
> > > However, one of the things I had to change was the dummy data sent
> > > out by SPI for read-only transactions.
This patch adds redundant environment for environment in SPI flash.
I took env_flash.c as an example and slightly modified it. Apart
from adapting things to SF, I also slightly changed the decision
logic to use area 2 as a default in case the flags are wrong because
not having a default path worrie
Hi Mike,
On Fri, Apr 23, 2010 at 11:08:10AM -0400, Mike Frysinger wrote:
> On Friday 23 April 2010 04:43:07 Wolfgang Wegner wrote:
> > However, one of the things I had to change was the dummy data sent
> > out by SPI for read-only transactions. The original driver had all
> > zeros, for SD/MMC all
On Fri, Apr 23, 2010 at 5:56 PM, Mike Frysinger wrote:
> On Friday 23 April 2010 10:10:16 Michael Zaidman wrote:
>> Compiling the bf537-stamp board I got the following linker error:
>> /home/mike/develop/u-boot/u-boot-patch/common/cmd_mmc.c:53: undefined
>> reference to `mmc_legacy_init'
>> /home/
for future reference, you shouldnt put "patch" in the subject name ... i'm not
referring to the leading [PATCH], but the trailing "patch".
also, i'm not sure if you're using `git send-email` because the trail of your
patch is missing the "---" marker:
=
It seems that fifo und
On Friday 23 April 2010 04:43:07 Wolfgang Wegner wrote:
> However, one of the things I had to change was the dummy data sent
> out by SPI for read-only transactions. The original driver had all
> zeros, for SD/MMC all ones (0xFF) is needed.
>
> Is such a change acceptable, or is there any configur
On Friday 23 April 2010 05:22:16 Wolfgang Wegner wrote:
> Signed-off-by: Wolfgang Wegner
> ---
> This patch adds redundant environment for environment in SPI flash.
> I took env_flash.c as an example and slightly modified it. Apart
> from adapting things to SF, I also slightly changed the decision
On Thursday 22 April 2010 23:42:13 macp...@andestech.com wrote:
> Since our toolchain haven’t been commit to GNU, could we commit code to
> u-boot before GNU accept our toolchain support?
yes, you can
> Is there anything special that we must provide to you?
the patches :p
-mike
signature.asc
D
From: Vaibhav Hiremath
This patch adds basic support for the AM3517EVM.
It includes:
- Board int file (.c and .h)
- Default configuration file
- Updates for Makefile
Signed-off-by: Vaibhav Hiremath
Signed-off-by: Sanjeev Premi
---
Makefile
From: Vaibhav Hiremath
Consolidated SDRC related functions into one file - sdrc.c
And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.
Signed-off-by: Vaibhav Hirem
From: Vaibhav Hiremath
This patch adds support for the EMIF4 interface
available in the AM35x processors.
Signed-off-by: Vaibhav Hiremath
Signed-off-by: Sanjeev Premi
---
arch/arm/cpu/arm_cortexa8/omap3/Makefile|3 +
arch/arm/cpu/arm_cortexa8/omap3/emif4.c | 168 +
From: Vaibhav Hiremath
The EVMS have been shipping with NAND (instead of OneNAND) as default.
So, this patch sets NAND as default.
To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
config file omap3_evm.h,
Changes from V3 :-
- Added undef statement for CMD_ONENAND.
Signe
From: Vaibhav Hiremath
The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.
Signed-off-by: Vaibhav Hiremath
Signed-off-by: Sanjeev Premi
---
arch/arm/cpu/arm_cortexa8/omap3/board.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
From: Vaibhav Hiremath
Changes from V1 (comments provided by Tom Rix):
- Refreshed against latest denx/master.
- Further split SDRC consolidated patch, since it was
fixing up one issue in dram_init in addition to code
moment.
- Retained copyright for sd
On Friday 23 April 2010 10:10:16 Michael Zaidman wrote:
> Compiling the bf537-stamp board I got the following linker error:
> /home/mike/develop/u-boot/u-boot-patch/common/cmd_mmc.c:53: undefined
> reference to `mmc_legacy_init'
> /home/mike/develop/u-boot/u-boot-patch/common/cmd_mmc.c:53: relocati
On Friday 23 April 2010 04:20:34 Wolfgang Wegner wrote:
> On Thu, Apr 22, 2010 at 11:28:27PM -0400, Mike Frysinger wrote:
> > +static short mmc_spi_init_card(struct mmc_spi_dev *pdev)
> > +{
> > + unsigned short cntr = 0;
> > +
> > + /* for making init process beeing silent */
> > + init_mode
2010/4/23 Gurumurthy G M :
>
>
> let me know if anyone have ported u-boot to MIPS32.
I did a couple of ports for Au1550 boards back when it was still owned by AMD.
On Au1550 if the boot pins are set up for NOR flash, the CS0 line is
mapped with a base physical address 0x0_1fc0_ (36 bit physic
Signed-off-by: Graeme Russ
---
arch/i386/include/asm/unaligned.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
create mode 100644 arch/i386/include/asm/unaligned.h
diff --git a/arch/i386/include/asm/unaligned.h
b/arch/i386/include/asm/unaligned.h
new file mode 100644
index 000
Shamelessly steal the Linux x86 crash handling code and shove it into
U-Boot (cool - it fits). Be sure to include suitable attribution to
Linus
Signed-off-by: Graeme Russ
---
arch/i386/cpu/interrupts.c | 310
1 files changed, 228 insertions(+), 82 de
There is an error in how the assembler version of the sc520 memory size
reporting code works. As a result, it will only ever report at most the
size of one bank of RAM
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520_asm.S | 35 +--
1 files changed, 17 i
Hi,
Compiling the bf537-stamp board I got the following linker error:
/home/mike/develop/u-boot/u-boot-patch/common/cmd_mmc.c:53: undefined
reference to `mmc_legacy_init'
/home/mike/develop/u-boot/u-boot-patch/common/cmd_mmc.c:53: relocation
truncated to fit: R_pcrel24 against undefined symbol `mmc
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520_asm.S |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S
index 3407254..c8f74b3 100644
--- a/arch/i386/cpu/sc520/sc520_asm.S
+++ b/arch/i386/cpu/sc520/
AMD recently changed the licensing of the RAM sizing code to the
GPLv2 (or at you option any later version)
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520_asm.S | 117 +-
1 files changed, 77 insertions(+), 40 deletions(-)
diff --git a/arch/i386/cpu
Signed-off-by: Graeme Russ
---
board/eNET/eNET.c | 46 ++
board/eNET/hardware.h |1 +
include/configs/eNET.h | 10 +-
3 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index ad71f
Signed-off-by: Graeme Russ
---
include/configs/eNET.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index dac3ede..6189794 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -160,7 +160,7 @@
* CPU Featu
The eNET uses the sc520 software timers rather than the PC/AT clones
Set all interrupts and timers up to be PC/AT compatible
Signed-off-by: Graeme Russ
---
board/eNET/eNET.c | 38 ++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/board/eNET
Signed-off-by: Graeme Russ
---
board/eNET/eNET.c |7 +++
include/configs/eNET.h |9 -
2 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 52ea140..62f99ce 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -24
The clock interupt has always been 1kHz as per timer_init() in
/arch/i386/cpu/sc520/sc520_timer.c
Signed-off-by: Graeme Russ
---
include/configs/eNET.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index f643f7f..0bfbd08
Signed-off-by: Graeme Russ
---
arch/i386/include/asm/ic/pci.h | 29 +
arch/i386/include/asm/ic/sc520.h | 29 -
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/i386/include/asm/ic/pci.h b/arch/i386/include/asm/ic/p
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520_pci.c | 39 ++-
arch/i386/include/asm/ic/pci.h |1 +
board/eNET/eNET_pci.c | 34 ++
3 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch
Onboard AMD Flash chip does not support buffered writes
Signed-off-by: Graeme Russ
---
include/configs/eNET.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 05d7db8..f643f7f 100644
--- a/include/configs/eNET.h
+++ b
If the board has a high precision mico-second timer, it maked sense to use
it instead of the on-chip one
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520_timer.c |4
arch/i386/include/asm/ic/sc520.h |1 +
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/i
Signed-off-by: Graeme Russ
---
arch/i386/cpu/Makefile |2 +-
arch/i386/cpu/serial.c | 506
arch/i386/lib/board.c |5 +-
board/eNET/eNET.c |3 +-
common/serial.c|3 +-
include/configs/eNET.h | 26 ++-
include/serial.
It is possibly to setup x86 boards to use non-PC/AT configurations. For
example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals.
This function allows the board to set itself up for maximum PC/AT
compatibility just before booting the Linux kernel (the Linux kernel
'just works' if every
The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access
the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped
and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and
drop the custom serial port driver
Signed-off-by: Graeme Russ
---
drive
Signed-off-by: Graeme Russ
---
arch/i386/lib/bios_setup.c |2 +-
arch/i386/lib/realmode.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/i386/lib/bios_setup.c b/arch/i386/lib/bios_setup.c
index 6491e52..a92b77e 100644
--- a/arch/i386/lib/bios_setup.c
+++ b/ar
In order to locate the 16-bit BIOS code, we need to know the reloaction
offset.
Signed-off-by: Graeme Russ
---
arch/i386/lib/board.c | 63 -
1 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/bo
Currently, the GDT is either located in FLASH or in the non-relocated
U-Boot image in RAM. Both of these locations are unsafe as those
locations can be erased during a U-Boot update. Move the GDT into the
highest available memory location and relocate U-Boot to just below it
Signed-off-by: Graeme
Add a parameter to the 32-bit entry to indicate if entry is from Real
Mode or not. If entry is from Real Mode, execute the destructive 'sizer'
routine to determine memory size as we are booting cold and running in
Flash. If not entering from Real Mode, we are executing a U-Boot image
from RAM and t
This patch allows the low-level assembler boot-strap to obtain the RAM
size without calling the destructive 'sizer' routine. This allows
boot-strapping from a U-Boot image loaded in RAM
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520_asm.S | 95 +++---
This was broken a long time ago by a49864593e083a5d0779fb9ca98e5a0f2053183d
which munged the NIOS and x86 do_go_exec()
Signed-off-by: Graeme Russ
---
arch/i386/lib/board.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.
Change sc520 MMCR Access to use memory accessor functions
Signed-off-by: Graeme Russ
---
arch/i386/cpu/sc520/sc520.c | 33 --
arch/i386/cpu/sc520/sc520_pci.c | 24 ++
arch/i386/cpu/sc520/sc520_ssi.c | 27 ++--
arch/i386/cpu/sc520/sc520_timer.c | 31 +
Signed-off-by: Graeme Russ
---
arch/i386/lib/board.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index f3b6348..af81cd5 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -280,8 +280,10 @@ void board_init_r
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Hello Everyone
Respin of a previous patch set addressing a few minor issues
including:
Version 2:
- Resolved the PCI_BASE_ADDRESS_1 --> PCI_BASE_ADDRESS_0 modification.
It turned out to be a PCI region definition issue where the existing
code was making non-generic assumptions about the allo
Fix MX51 CPU detect message.
Original string was:
CPU: Freescale i.MX51 family 3.0V at 800 MHz
which can be misinterpreted as 3.0 Volts instead of the silicon revision.
,change it to:
CPU: Freescale i.MX51 family rev3.0 at 800 MHz
Signed-off-by: Fabio Estevam
---
arch/arm/cpu/arm_corte
> -Original Message-
> From: Tom Rix [mailto:t...@bumblecow.com]
> Sent: Thursday, April 22, 2010 5:17 AM
> To: Prafulla Wadaskar
> Cc: u-boot@lists.denx.de; Siddarth Gore; Tom Rix
> Subject: Re: [U-Boot] Pull request u-boot-marvell.git
>
> Prafulla Wadaskar wrote:
> > Hi Tom
> >
> >
This patch adds bootcount for Freescale MCF5445x. Two registers of
eDMA transfer control descriptors (TCD[1]) are used because these
are unused by linux kernel (freescale LTIB linux-2.6.25) and were
tested to keep their contents across resets.
Signed-off-by: Wolfgang Wegner
---
I implemented and
Liu Hui-R64343 wrote:
> Stefano ,
>
Hi Jason,
>>
>> +#define CONFIG_SYS_DDR_CLKSEL 0
>> +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
>
> It's nice to have some comments about the value selected.
This patch is more as one month old and was already merged into the
mainline, so we need
Dne Pá 23. dubna 2010 05:42:13 macp...@andestech.com napsal(a):
> Hi Wolfgang,
>
>
>
> I’m working for Andestech, which is a RISC IP (NDS32) company in Taiwan.
>
> This company has been started for 5 years.
>
> In recent , we are planning to release source code such as Linux Kernel and
> GNU t
Hello Wolfgang,
Wolfgang Denk wrote:
> In message <4bc2ccbe.6060...@denx.de> you wrote:
>> - serial console on UART1
>> - Ethernet RMII over UCC4
>> - PHY SMSC LAN8700
>> - 64MB Flash
>> - 128 MB DDR2 RAM
>> - I2C
>> - bootcount
>>
>> This board is similiar to the kmeter1 (8360) board,
>> so commo
Ben,
I have a specific question on the way we handle phy address
in SPEAr.
>> +
>> +static u8 find_phy(struct eth_device *dev)
>> +{
>> +u8 phy_addr = 0;
>> +u16 ctrl, oldctrl;
>> +
>> +do {
>> +eth_mdio_read(dev, phy_addr, PHY_BMCR,&ctrl);
>> +oldctrl = ctrl&
Excuse me, I forgot to paste in the u-boot output:
=> nand info
Device 0: nand0, sector size 128 KiB
=> nand erase
NAND erase: device 0 whole chip
Bad block table found at page 524224, version 0x01
Bad block table found at page 524160, version 0x01
nand_read_bbt: Bad block at 0x006c
nan
I'm using a MPC8572DS evaluation system and attempting to set up a UBI
file system from u-boot. I've seen a similar thread with similar errors
but my error isn't being caused by the define CONFIG_SYS_MALLOC_LEN
being too small (it's set for 1M).
I'm just starting with UBI/UBIFS and hoping someon
Hi!
It seems like the layout of OOB/4-Bit-ECC data in NAND flash differs from
RBL/UBL to u-boot/linux (at least on a DM365 device). Is there any good reason
for this?
As far as I understand, the RBL/UBL uses this layout (2048 byte pages):
(E = ECC byte, X = other oob)
XXEE
XX
Stefano ,
> -Original Message-
> From: u-boot-boun...@lists.denx.de
> [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Stefano Babic
> Sent: 2010年3月28日 19:43
> To: u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH V2] Moved board specific values in
> config file
>
> The lowlevel_init fi
Dear Gurumurthy G M,
please do not top post / full quote.
And do not ask questions you have just asked a few hours before.
In message <5858de952c53a441bda3408a0524130104cce...@mkegmal01> you wrote:
>
>
> let me know if anyone have ported u-boot to MIPS32.
Why don't you have a look yourself at
Dear Anatolij,
In message <20100423102809.5afa8...@wker> you wrote:
>
> > [I'll leave this code as is in the u-boot-mpc5xxx repo for now, but I
> > will rebase this as soon as you submit a fix.]
>
> What would be the best way to proceed here? I submitted separate
> patch to fix this, "serial: fi
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