andom seed to fdt
Stafford Horne (10):
hw/openrisc: Split re-usable boot time apis out to boot.c
target/openrisc: Fix memory reading in debugger
goldfish_rtc: Add big-endian property
hw/openrisc: Add the OpenRISC virtual machine
hw/openrisc: Add PCI bus support to virt
hw/openrisc: Initi
C SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
configs/devices/or
. Global cpu timer (last_clk and ttcr) reset, attached to the first
cpu only.
Signed-off-by: Stafford Horne
---
Since v2:
- Moved timer init from init to reset suggested by Richard
hw/openrisc/cputimer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git
: Stafford Horne
---
Since v2:
- Added Reviewed-by
target/openrisc/cpu.c| 1 -
target/openrisc/sys_helper.c | 7 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/boot.c | 117 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106
protection mapping then falling back to PAGE_EXEC.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes, added Reviewed-by
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/m
When we are tracing it's helpful to know which CPU's are getting
interrupted, add that detail to the log line.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+),
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/Kconfig | 3 +
hw
Donenfeld
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index 9a78234a28..f8a68a6a6b 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt
ent Vivier
Reviewed-by: Anup Patel
Signed-off-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
- Changed from enum property to boolean as suggested by Richard
hw/m68k/virt.c| 1 +
hw/rtc/goldfish_rtc.c | 37 ++-
include/hw/rtc/gold
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
Since v2:
- Removed cpu_openrisc_timer_has_advanced lock optimization, measuring revealed
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2;
- Added Reviewed-by
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst
On Fri, Jul 29, 2022 at 04:42:54PM -0700, Richard Henderson wrote:
> On 7/29/22 16:01, Stafford Horne wrote:
> > This patch enables multithread TCG for OpenRISC. Since the or1k shared
> > syncrhonized timer can be updated from each vCPU via helpers we use a
> > mutex t
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Signed-off-by: Stafford Horne
---
target/
On Sat, Jul 29, 2023 at 10:08:51PM +0100, Stafford Horne wrote:
> The architecture specification calls for the EPCR to be set to "Address
> of next not executed instruction" when there is a floating point
> exception (FPE). This was not being done, so fix it by using the same
On Sun, Jul 30, 2023 at 10:43:45AM -0700, Richard Henderson wrote:
> On 7/29/23 14:08, Stafford Horne wrote:
> > The architecture specification calls for the EPCR to be set to "Address
> > of next not executed instruction" when there is a floating point
> > excep
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Reviewed-by: Richard Henderson
Signe
;version
> > 2.0" of the "Lesser" license. So assume that version 2.1 is meant here.
Acked-by: Stafford Horne
> > Signed-off-by: Thomas Huth
> > ---
> > hw/openrisc/cputimer.c | 2 +-
> > hw/openrisc/openrisc_sim.c | 2 +-
>
On Thu, Jun 06, 2019 at 07:01:49PM +0200, Markus Armbruster wrote:
Stafford Horne writes:
On Mon, Jun 03, 2019 at 10:45:14AM +0200, Philippe Mathieu-Daudé wrote:
On 5/31/19 5:36 AM, Stafford Horne wrote:
> On Wed, May 29, 2019 at 05:08:52PM +0200, Markus Armbruster wrote:
>> Whe
On Tue, Mar 12, 2019 at 06:36:05PM +0100, Markus Armbruster wrote:
> = hw/openrisc/openrisc_sim.c =
> Jia Liu (maintainer:or1k-sim)
> Stafford Horne (odd fixer:OpenRISC)
For OpenRISC the main test I do is booting linux. The steps and a link to a
system image are descr
ris/cpu_loop.c
> - linux-user/hppa/syscall_nr.h
> - linux-user/openrisc/syscall_nr.h
> - linux-user/tilegx/syscall_nr.h
>
> CC: Edgar E. Iglesias
> CC: Richard Henderson
> CC: Stafford Horne
>
> Again, I don't plan (I am really running out of time resources) to
>
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
---
Since v1
as no-ops as the cpu implementations do. As mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
---
Since v1:
- Use function do_fpe (similar to do_range) to raise exception.
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
---
Since v1:
- Remove setting default NaN behavior. I discussed with the FPU developers and
they mentioned the OpenRISC hardware should be IEEE compliant when handling
and
On Wed, May 10, 2023 at 05:13:03PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong
> > rb)
> > {
> > -#ifndef CONFIG_USER_ONLY
> > OpenRISCCPU *cpu
On Wed, May 10, 2023 at 05:16:20PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > OpenRISC defines tininess to be detected before rounding. Setup qemu to
> > obey this.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > Since
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
Since v2:
- Add reviewed-by
Since v1:
- Use function do_fpe (similar to do_range) to raise exception.
target/openrisc/fpu_helper.c | 13
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed-by
math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target/openrisc: Setup FPU for detecting tininess before rounding
target/openrisc/cpu.c| 4 ++
target/openrisc/fpu_helper.c
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
Since v2:
- Add reviewed-by
Since v1:
- Remove setting default NaN behavior.
target/openrisc/cpu.c | 4
1 file changed, 4 insertions
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/fpu_helper.c b/target
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed-by
architecture spec updates:
- Allow FPCSR to be accessed in user mode
- Select tininess detection before rounding
- Fix FPE Exception PC value
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc
n Linux 5.19-rc2.
>
> Cc: Stafford Horne
> Signed-off-by: Jason A. Donenfeld
> ---
> Changes v1->v2:
> - This is rebased on top of your "or1k-virt-2" branch.
> - It makes the change to the new "virt" platform, since that's where it
> makes
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 117 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++---
include
protection mapping then falling back to PAGE_EXEC.
Signed-off-by: Stafford Horne
---
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
++
.
Changes since v1:
- Dropped semihosting support
- Added PCI support
- Added OpenRISC documentation
- Added OpenRISC support for MTTCG
- Support Configurating Goldfish RTC endianness
- Added a few bug fix patches
-Stafford
Jason A. Donenfeld (1):
hw/openrisc: virt: pass random seed to fdt
Add an endianness property to allow configuring the RTC as either
native, little or big endian.
Cc: Laurent Vivier
Signed-off-by: Stafford Horne
---
hw/rtc/goldfish_rtc.c | 46 ---
include/hw/rtc/goldfish_rtc.h | 2 ++
2 files changed, 39 insertions
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160
The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.
Initialize last_clk to the qemu clock on initialization.
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 1 +
1 file
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/targe
C SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak |
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/cputimer.c | 17
not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Signed-off-by: Stafford Horne
---
target/openrisc
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Stafford Horne
Signed-off
Signed-off-by: Stafford Horne
---
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst | 50 +++
docs/system/target-openrisc.rst
On Mon, Jul 04, 2022 at 03:34:52PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > When we are tracing it's helpful to know which CPU's are getting
> > interrupted, att that detail to the log line.
>
> "at".
>
> Reviewe
On Mon, Jul 04, 2022 at 03:37:04PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > case TO_SPR(10, 1): /* TTCR */
> > -cpu_openrisc_count_update(cpu);
> > +if (cpu_openrisc_timer_has_advanced(cpu)) {
> > +
On Mon, Jul 04, 2022 at 03:33:26PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > The last_clk time was initialized at zero, this means when we calculate
> > the first delta we will calculate 0 vs current time which could cause
>
On Mon, Jul 04, 2022 at 03:29:57PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > -static const MemoryRegionOps goldfish_rtc_ops = {
> > -.read = goldfish_rtc_read,
> > -.write = goldfish_rtc_write,
> > -.endianness = DEVICE_NAT
On Mon, Jul 04, 2022 at 12:23:23PM +0200, Laurent Vivier wrote:
> On 04/07/2022 12:21, Richard Henderson wrote:
> > On 7/4/22 15:46, Laurent Vivier wrote:
> > > On 04/07/2022 11:59, Richard Henderson wrote:
> > > > On 7/4/22 02:58, Stafford Horne wrote:
> >
mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
---
target/openrisc/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa..cdbff26fb5 100644
--- a/target
instruction exception is not part of the spec, so this should be OK.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
---
target/openrisc/sys_helper.c | 45 +-
target/openrisc/translate.c | 72
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
---
target/openrisc/fpu_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..1feebb9ac7 100644
On Tue, May 02, 2023 at 07:57:29PM +0100, Stafford Horne wrote:
> As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
>
> Update mtspr and mfspr helpers to support this by moving the is_user
> check into the helper.
>
> There is a logic change here to no longe
On Wed, May 03, 2023 at 08:36:13AM +0100, Richard Henderson wrote:
> On 5/2/23 19:57, Stafford Horne wrote:
> > @@ -55,6 +56,9 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
> > if (tmp) {
> > env->fpcsr |= tmp;
> >
On Wed, May 03, 2023 at 08:37:31AM +0100, Richard Henderson wrote:
> On 5/2/23 19:57, Stafford Horne wrote:
> > OpenRISC defines tininess to be detected before rounding. Setup qemu to
> > obey this.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > targe
On Wed, May 03, 2023 at 10:41:42AM +0100, Richard Henderson wrote:
> On 5/3/23 10:14, Stafford Horne wrote:
> > > > +set_default_nan_mode(1, &cpu->env.fp_status);
> > > > +set_float_detect_tininess(float_tininess_before_rounding,
> > > > +
risc
> + ~ (/qemu)?((/include)?/hw/openrisc/.*|/target/openrisc/.*)
This looks good to me for OpenRISC. Where can we view the coverity reports?
Is it this?: https://scan.coverity.com/projects/378
Acked-by: Stafford Horne
> +xtensa
> + ~ (/qemu)?((/include)?/hw/xtensa/.*|/target/xtensa/.*)
The initrd passed via the command line is loaded into memory. It's
location and size is then added to the device tree so the kernel knows
where to find it.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
hw/openrisc/openrisc_sim.c | 31 +++
1
eration to openrisc_sim
----
Stafford Horne (6):
hw/openrisc/openrisc_sim: Create machine state for or1ksim
hw/openrisc/openrisc_sim: Parameterize initialization
hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UAR
Now that we no longer have a limit of 2 CPUs due to fixing the
IRQ routing issues we can increase the max. Here we increase
the limit to 4, we could go higher, but currently OMPIC has a
limit of 4, so we align with that.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
Reviewed-by
Move magic numbers to variables and enums. These will be reused for
upcoming fdt initialization.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 42 ++
1 file changed, 34 insertions(+), 8 deletions(-)
diff
This patch moves serial initialization out to it's own function and
uses a splitter to connect multiple CPU irq lines to the UART.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 32
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc
the state of the
configure openrisc simulator.
This is then dumped to memory and the load address is passed to the
kernel in register r3.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/openrisc_sim.c | 189
On Fri, Feb 25, 2022 at 01:52:52PM +, Peter Maydell wrote:
> On Fri, 25 Feb 2022 at 09:19, Stafford Horne wrote:
> >
> > The following changes since commit 4aa2e497a98bafe962e72997f67a369e4b52d9c1:
> >
> > Merge remote-tracking branch
> > 'remot
eration to openrisc_sim
Since v1:
- Added fdt file include into meson.build
- I couldn't figure out how to run CI easily, so but I think this is the right
fix.
Stafford Horne (6):
hw/openrisc/openrisc_sim: Create machine st
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc
Now that we no longer have a limit of 2 CPUs due to fixing the
IRQ routing issues we can increase the max. Here we increase
the limit to 4, we could go higher, but currently OMPIC has a
limit of 4, so we align with that.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
Reviewed-by
Move magic numbers to variables and enums. These will be reused for
upcoming fdt initialization.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 42 ++
1 file changed, 34 insertions(+), 8 deletions(-)
diff
This patch moves serial initialization out to it's own function and
uses a splitter to connect multiple CPU irq lines to the UART.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 32
the state of the
configure openrisc simulator.
This is then dumped to memory and the load address is passed to the
kernel in register r3.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
Since v1:
- Added fdt to CONFIG_OR1K_SIM source set
configs/targets/or1k-softmmu.mak | 1 +
hw
The initrd passed via the command line is loaded into memory. It's
location and size is then added to the device tree so the kernel knows
where to find it.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
hw/openrisc/openrisc_sim.c | 31 +++
1
for looking into it. I am happy to accept kernel patches ;), otherwise
these are now on my todo list. The FPU support is already something I am
looking to take care of as mentioned before, but that is after I finish getting
the glibc port upstreamed.
That said,
Reviewed-by: Stafford Horne
&
The loaded initrd is loaded into memory. It's location and size is then
added to the device tree so the kernel knows where to find it.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff
configure
openrisc simulator.
This is then dumpt to memory and the load address is passed to the
kernel in register r3.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 158 -
1 file changed, 154 insertions(+), 4 deletions(-)
diff --git a/hw/openrisc
Move magic numbers to variables and enums. These will be
reused for upcoming fdt initialization.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 42 ++
1 file changed, 34 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc
where to find it.
-Stafford
Stafford Horne (4):
hw/openrisc/openrisc_sim: Create machine state for or1ksim
hw/openrisc/openrisc_sim: Paramatarize initialization
hw/openrisc/openrisc_sim; Add support for loading a decice tree
hw/openrisc/openrisc_sim: Add support for initrd loading
hw
gnal(env, info.si_signo, QEMU_SI_FAULT, &info);
> +force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
> break;
> case EXCP_ATOMIC:
> cpu_exec_step_atomic(cs);
This looks ok to me.
Reviewed-by: Stafford Horne
s the bug, because it meant when execution resumed
after the interrupt was handling it resumed in the wrong place.
Fix this by implementing synchronize_from_tb which simply updates pc,
and not clear the delay slot flag.
Reported-by: Jason A. Donenfeld
Signed-off-by: Stafford Horne
---
target/ope
| 2 +-
> tcg/tcg-internal.h| 2 +-
> 20 files changed, 20 insertions(+), 20 deletions(-)
I looked at this for the OpenRISC changes, but the whole patch looks ok to me.
Reviewed-by: Stafford Horne
On Wed, May 11, 2022 at 07:32:58AM -0700, Richard Henderson wrote:
> On 5/11/22 05:05, Stafford Horne wrote:
> > +static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
> > + const TranslationBlock *tb)
> > +{
> > +Open
On Wed, May 11, 2022 at 02:56:37PM -0700, Richard Henderson wrote:
> On 5/11/22 14:43, Stafford Horne wrote:
> > At this point how would tb->flags have the right value? Would it always be
> > set
> > correctly by `cpu_get_tb_cpu_state` in the `lookup_tb_ptr`call?
>
On Wed, May 11, 2022 at 07:11:20PM -0700, Richard Henderson wrote:
> On 5/11/22 15:34, Stafford Horne wrote:
> > In this case I don't see how the tb->flag would be updated, ooh, I guess it
> > would have been set earlier when the TB was generated. Maybe that is wha
e variable
Stafford Horne (1):
target/openrisc: Do not reset delay slot flag on early tb exit
hw/openrisc/openrisc_sim.c | 28 +++-
target/openrisc/cpu.c | 11 +++
2 files changed, 30 insertions(+), 9 deletions(-)
Jason A. Donenfeld (3):
hw/openrisc:
From: "Jason A. Donenfeld"
The QEMU-provided FDT was only being recognized by the kernel when it
was used in conjunction with -initrd. Without it, the magic bytes
wouldn't be there and the kernel couldn't load it. This patch fixes the
issue by page aligning the provided FDT.
on A. Donenfeld
[smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX]
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 6873124f74..35adce17ac 100644
--
From: "Jason A. Donenfeld"
The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.
Cc: Stafford Horne
Signed-off-by: Jason A. Donenfeld
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horn
ff-by: Stafford Horne
---
target/openrisc/cpu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index dfbafc5236..41d1b2a24a 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
On Sun, May 15, 2022 at 04:12:50PM -0700, Richard Henderson wrote:
> On 5/14/22 18:39, Stafford Horne wrote:
> > The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
> >
> >Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qem
On Thu, Feb 10, 2022 at 12:05:22PM +0100, Philippe Mathieu-Daudé wrote:
> On 10/2/22 07:30, Stafford Horne wrote:
> > This will allow us to attach machine state attributes like
> > the device tree fdt.
> >
> > Signed-off-by: Stafford Horne
> > ---
>
On Thu, Feb 10, 2022 at 12:07:02PM +0100, Philippe Mathieu-Daudé wrote:
> On 10/2/22 07:30, Stafford Horne wrote:
> > Move magic numbers to variables and enums. These will be
> > reused for upcoming fdt initialization.
> >
> > Signed-off-by: Stafford Horne
Move magic numbers to variables and enums. These will be reused for
upcoming fdt initialization.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 42 ++
1 file changed, 34 insertions(+), 8 deletions(-)
diff
The initrd passed via the command line is loaded into memory. It's
location and size is then added to the device tree so the kernel knows
where to find it.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 32 +++-
1 file changed, 31 insertions(
configure
openrisc simulator.
This is then dumped to memory and the load address is passed to the
kernel in register r3.
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/openrisc_sim.c | 159 ++-
2 files changed, 156 insertions
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