Hello, This is the OpenRISC Virtual Machine plaform which we are now using for OpenRISC CI such as the wireguard testing that Jason has been working on. I also have recently used it to test glibc 2.36 and it worked well. Previous glibc testsuite runs on my FPGA board took about 3 days, running on qemu virt now takes 6 hours.
The first few patches help get OpenRISC QEMU ready for the virtual machine. There is one bug fix for GDB debugging there too. Next we have the Virt patch followed by a separate patch to add PCI support which is split out because it's a bit easier to review that way I thought. The next few patches are fixes to get the Multicore platform stable, such as adding MTTCG support and fixing some interrupt and timer related bugs. The platform is relatively stable now, but every few boots we get about 10 second hangs. However, overall this is much more stable than the SMP support we had before. So I want to submit this for review and maybe upstream it before tracking down these last issues which might take significant more time. This is being tested with the or1k-5.20-updates kernel branch here: https://github.com/stffrdhrn/linux/commits/or1k-5.20-updates This tree has support for: OpenRISC PCI and virt_defconfig and an irqchip bug fix. Changes since v2: - Changed goldfish_rtc endian property to boolean - Moved or1k timer init from init to reset - Removed cpu_openrisc_timer_has_advanced lock optimization in MTTCG patch, measuring revealed it did not help much. Changes since v1: - Dropped semihosting support - Added PCI support - Added OpenRISC documentation - Added OpenRISC support for MTTCG - Support Configurating Goldfish RTC endianness - Added a few bug fix patches Jason A. Donenfeld (1): hw/openrisc: virt: pass random seed to fdt Stafford Horne (10): hw/openrisc: Split re-usable boot time apis out to boot.c target/openrisc: Fix memory reading in debugger goldfish_rtc: Add big-endian property hw/openrisc: Add the OpenRISC virtual machine hw/openrisc: Add PCI bus support to virt hw/openrisc: Initialize timer time at startup target/openrisc: Add interrupted CPU to log target/openrisc: Enable MTTCG target/openrisc: Interrupt handling fixes docs/system: openrisc: Add OpenRISC documentation configs/devices/or1k-softmmu/default.mak | 1 + configs/targets/or1k-softmmu.mak | 1 + docs/system/openrisc/cpu-features.rst | 15 + docs/system/openrisc/emulation.rst | 17 + docs/system/openrisc/or1k-sim.rst | 43 ++ docs/system/openrisc/virt.rst | 50 ++ docs/system/target-openrisc.rst | 72 +++ docs/system/targets.rst | 1 + hw/m68k/virt.c | 1 + hw/openrisc/Kconfig | 12 + hw/openrisc/boot.c | 117 +++++ hw/openrisc/cputimer.c | 22 +- hw/openrisc/meson.build | 2 + hw/openrisc/openrisc_sim.c | 106 +---- hw/openrisc/virt.c | 571 +++++++++++++++++++++++ hw/rtc/goldfish_rtc.c | 37 +- include/hw/openrisc/boot.h | 34 ++ include/hw/rtc/goldfish_rtc.h | 2 + target/openrisc/cpu.c | 1 - target/openrisc/cpu.h | 2 + target/openrisc/interrupt.c | 4 +- target/openrisc/mmu.c | 8 +- target/openrisc/sys_helper.c | 14 +- 23 files changed, 1019 insertions(+), 114 deletions(-) create mode 100644 docs/system/openrisc/cpu-features.rst create mode 100644 docs/system/openrisc/emulation.rst create mode 100644 docs/system/openrisc/or1k-sim.rst create mode 100644 docs/system/openrisc/virt.rst create mode 100644 docs/system/target-openrisc.rst create mode 100644 hw/openrisc/boot.c create mode 100644 hw/openrisc/virt.c create mode 100644 include/hw/openrisc/boot.h -- 2.37.1
