On Mon, Aug 06, 2012 at 01:07:15PM +1000, Peter A. G. Crosthwaite wrote:
> Re-implemented the interconnect between the Xilinx AXI ethernet and DMA
> controllers. A QOM interface "stream" is created, for the two stream
> interfaces.
>
> As per Edgars request, this is designed to be more generic th
On Fri, Aug 10, 2012 at 01:16:09PM +1000, Peter A. G. Crosthwaite wrote:
> The following changes since commit 3d1d9652978ac5a32a0beb4bdf6065ca39440d89:
> Bruce Rogers (1):
> handle device help before accelerator set up
>
> are available in the git repository at:
>
> git://developer.pe
On Mon, Aug 13, 2012 at 06:50:43PM +0200, Andreas Färber wrote:
> Hej Edgar,
>
> Am 13.08.2012 11:41, schrieb Edgar E. Iglesias:
> > On Fri, Aug 10, 2012 at 01:16:09PM +1000, Peter A. G. Crosthwaite wrote:
> >> The following changes since commit
> >> 3d1d965
On Sat, Jan 28, 2012 at 11:48:37AM -0700, Grant Likely wrote:
> On Fri, Jan 27, 2012 at 10:34:01PM +, Paul Brook wrote:
> > > If compiled with CONFIG_FDT, allow user to specify a device tree file
> > > using
> > > the -dtb argument. If the machine supports it then the dtb will be loaded
> > >
arnings in zynq_arm_sysctl (4/4)
> changes from v1:
> formatting and style fixes
> updated for QOM
> removed former patch 3 (cadence WDT device model) - not required
> removed former patch 5 (dtb argument) - this is currently under discussion in
> other patch series'
>
On Fri, Oct 19, 2012 at 12:59:49PM +0100, Peter Maydell wrote:
> On 19 October 2012 07:40, Peter Crosthwaite
> wrote:
> > From: Edgar E. Iglesias
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> >
> > hw/nand.c |6 ++
> > 1 files chang
On Fri, Oct 26, 2012 at 05:03:04PM +1000, Peter Crosthwaite wrote:
> In my recent USB series Avi mentioned he wanted to do some work with
> the memory API and encourage devices to use the memory API to do
> fine-grained register decoding, i.e. each register is its own
> MemoryRegion. This has the a
On Mon, Oct 29, 2012 at 06:34:37PM +0200, Avi Kivity wrote:
> On 10/29/2012 01:37 AM, John Williams wrote:
>
> >> IMO, an mr per reg would just add a massive overhead for no win.
> >
> > I tend to agree with Edgar here - QEMU has a careful line to walk between
> > being an emulator and an RTL si
On Sat, Jun 16, 2012 at 03:20:57PM +1000, Peter A. G. Crosthwaite wrote:
> Patch 1 is trival, just deleted a redundant include that shouldn't be there.
> Patch 2 is a major bugfix for Microblaze platforms - the timer was deadlocking
> the system.
>
> Peter A. G. Crosthwaite (2):
> xilinx_timer:
On Tue, Jun 26, 2012 at 02:29:39PM +1000, Peter A. G. Crosthwaite wrote:
> Set some missing maintainer ships. Patch 1 is the Petalogix ML605 machine
> model (me). Patch 2 is the Xilinx EDK device suite (me + Edgar). Patch 3 is
> the device tree subsystem (me + Alex).
Applied, Thanks!
>
> Ch
On Thu, Jun 28, 2012 at 02:53:13PM +0200, Andreas Färber wrote:
> Am 16.06.2012 03:11, schrieb Edgar E. Iglesias:
> > On Fri, Jun 15, 2012 at 01:30:17PM +0200, Andreas Färber wrote:
> >> Am 13.06.2012 06:46, schrieb Peter A. G. Crosthwaite:
> >>> Changed device nam
On Fri, Jun 29, 2012 at 01:31:01PM +1000, Peter Crosthwaite wrote:
> Hi Edgar,
>
> I think for little ones like this, ill start a microblaze-devs patch
> queue and periodically send pull requests. Ill send the patches singly
> to qemu-devel for ACK and NACK as I create them, then [PULL] every
> co
On Wed, Dec 05, 2012 at 04:53:41PM +1000, Peter Crosthwaite wrote:
> Minor fixes to xilinx microblaze IP.
>
> Peter Crosthwaite (3):
> xilinx_axienet: Implement R_IS behaviour
> xilinx_uartlite: suppress "cannot receive message"
> xilinx_uartlite: Accept input after rx FIFO pop
>
> hw/xili
On Wed, Jan 23, 2013 at 04:15:24PM +, Grant Likely wrote:
> Hopefully I've responded to everyone's comments here. Edgar, I did end
> up fixing up xilinx_axienet, so can you take a look and make sure it is
> correct?
It was something like that I had in mind, thanks.
gt; Cc: Paul Brook
> Cc: Edgar E. Iglesias
> Cc: Anthony Liguori
> Cc: Andreas Färber
> Signed-off-by: Grant Likely
> ---
> hw/etraxfs_eth.c | 922
> +++---
> 1 file changed, 466 insertions(+), 456 deletions(-)
>
>
On Thu, Jan 24, 2013 at 10:51:47AM +0100, Andreas Färber wrote:
> It's __VAR_ARGS__. Fixes the build with CRIS_[OP_]HELPER_DEBUG defined.
>
> Broken since r6338 / 93fcfe39a0383377e647b821c9f165fd927cd4e0 (Convert
> references to logfile/loglevel to use qemu_log*() macros).
Applied, thanks!
>
>
Sorry for reposting,
My email client freaked out when posting the first reply...
- Forwarded message from "Edgar E. Iglesias"
-
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On Thu, Jan 24, 2013 at 02:21:09PM +, Paul Brook wrote:
> > > > It also worries me that there isn't a clean separation between the MDIO
> > > > bus and the bitbang interface. IMO the bitbang interface should be a
> > > > separate device, and if we're wiring up bitbang interfaces then it
> > >
On Sat, Jan 26, 2013 at 12:18:29PM -0800, Peter Crosthwaite wrote:
> Hi All,
>
> Have a bit of a tricky question about ethernet controllers. We are
> maintaining two ethernet controllers the cadence GEM and the Xilinx AXI
> Ethernet both of which are scatter gather (SG) DMA capable. The issue co
On Fri, Jan 25, 2013 at 06:00:36PM +, Paul Brook wrote:
> > To be able to create generic GPIO devices or other devices that have GPIO
> > like pins (e.g MDIO), and hook those up to external buses through common
> > frameworks, we need agreement on how to model tristate pins.
> > A tristate pin
On Fri, Jan 25, 2013 at 05:58:38PM -0800, Peter Crosthwaite wrote:
> Default to moving back to the IDLE state after the COLLECTING_DATA
> state. For a well behaved guest this patch has no consequence, but
> A bad guest could crash QEMU by using one of the erase commands
> followed by a longer than
On Sat, Jan 26, 2013 at 12:36:22PM -0800, Peter Crosthwaite wrote:
> The eth_can_rx() function only checks the first buffers status ("ping"). The
> controller should be able to receive into "pong" when ping-pong is enabled.
> Checks the active buffer (either "ping" or "pong") when determining can_r
On Sat, Jan 26, 2013 at 12:36:23PM -0800, Peter Crosthwaite wrote:
> Software services a received packet by clearing the CTRL_S bit in the RX_CTRLn
> register. If this bit is cleared, flush any packets queued for the device.
Applied
>
> Reported-by: John Williams
> Signed-off-by: Peter Crosthwa
On Sat, Jan 26, 2013 at 12:36:24PM -0800, Peter Crosthwaite wrote:
> Some printfs are throwing warnings when debug mode is enabled. Fixed.
I committed a slightly different version using TARGET_FMT_plx and %zd
>
> Signed-off-by: Peter Crosthwaite
> ---
> hw/xilinx_ethlite.c | 10 ++
> 1
On Mon, Feb 04, 2013 at 02:42:55PM +0100, Andreas Färber wrote:
> Am 27.01.2013 07:26, schrieb Andreas Färber:
> > Around r3361 (81fdc5f8d2d681da8d255baf0713144f8656bac9) env->debug1 used
> > to contain the address of an MMU fault. This is now written into
> > env->pregs[PR_EDA] instead.
> >
> > S
On Sat, Feb 02, 2013 at 11:40:01PM +, Grant Likely wrote:
> Hi Edgar,
>
> Here is one more version of this patch set. I've addressed as many
> comments as I could. There is more work to be done, particularly in
> moving to the common GPIO api, but that work can be done as a follow on
> patch s
pu ? and -M axis-dev88 test image. Please ack.
>
> Available for testing from:
> git://github.com/afaerber/qemu-cpu.git qom-cpu-cris-classes.v2
> https://github.com/afaerber/qemu-cpu/commits/qom-cpu-cris-classes.v2
>
> Regards,
> Andreas
>
> Cc: Edgar E. Iglesias
A
Signed-off-by: Kuo-Jung Su
> Cc: Peter Crosthwaite
> Cc: Peter Maydell
> Cc: Edgar E. Iglesias
Applied, thanks!
> ---
> Changes for v3:
>- remove s->state = STATE_IDLE in complete_collecting_data()
>
> Changes for v2:
>- coding style fix
>
> hw/m2
Cleanup patch is ok with me.
Acked-by: Edgar E. Iglesias
---
Sent from my phone
On Feb 15, 2013 12:24 AM, "Andreas Färber" wrote:
>
> Am 14.02.2013 22:42, schrieb Blue Swirl:
> > On Thu, Feb 14, 2013 at 3:46 PM, Andreas Färber
wrote:
> >> Am 27.01.201
On Wed, Sep 26, 2012 at 04:27:57PM +1000, Peter Crosthwaite wrote:
> Hi All,
>
> Can anyone think of a reason why the arm primary bootloader cant be
> done by just direct interaction with the CPU? Currently we have this
> ...
>
> /* The worlds second smallest bootloader. Set r0-r2, then jump to
On Thu, Oct 04, 2012 at 12:36:04PM +0200, Avi Kivity wrote:
> The hassle and compile time overhead of maintaining both 32-bit and 64-bit
> capable source isn't worth the tiny performance advantage which is seen on
> a minority of configurations. Switch to compiling libhw only once, with
> target_p
On Mon, Oct 08, 2012 at 03:53:37PM -0500, Anthony Liguori wrote:
> Peter Maydell writes:
>
> > On 8 October 2012 21:23, Anthony Liguori wrote:
> >> It may be possible to cheat and compile the TCG + CPU code multiple
> >> times as dynamic libraries. You can then load the libraries with
> >> dlop
On Wed, Oct 10, 2012 at 10:46:33AM +1000, Peter Crosthwaite wrote:
> The following changes since commit 4bb26682f70a5f626cad3e0ac82bf4b6252ea7a4:
> Blue Swirl (1):
> Merge branch 'master' of git.qemu.org:/pub/git/qemu
>
> are available in the git repository at:
>
> git://developer.pet
On Tue, Oct 09, 2012 at 09:56:15PM +0200, Aurelien Jarno wrote:
> Rename helper flags to the new ones. This is purely a mechanical change,
> it's possible to use better flags by looking at the helpers.
>
> Cc: Edgar E. Iglesias
> Signed-off-by: Aurelien Jarno
Looks goo
On Tue, Oct 09, 2012 at 09:56:17PM +0200, Aurelien Jarno wrote:
> Rename helper flags to the new ones. This is purely a mechanical change,
> it's possible to use better flags by looking at the helpers.
>
> Cc: Edgar E. Iglesias
> Signed-off-by: Aurelien Jarno
Acked-b
On Tue, Oct 09, 2012 at 09:56:15PM +0200, Aurelien Jarno wrote:
> Rename helper flags to the new ones. This is purely a mechanical change,
> it's possible to use better flags by looking at the helpers.
>
> Cc: Edgar E. Iglesias
> Signed-off-by: Aurelien Jarno
> ---
Thanks Stefan. Ill apply this when i get back to swe in a couple of days.
Cheers
---
Sent from my phone
On Sep 3, 2012 10:46 PM, "Stefan Weil" wrote:
> Report from smatch:
>
> target-cris/translate.c:3464 cpu_dump_state(32) error:
> buffer overflow 'env->sregs' 4 <= 255
>
> sregs is declared '
On Tue, Sep 04, 2012 at 07:45:52AM +0200, Stefan Weil wrote:
> Report from smatch:
>
> target-cris/translate.c:3464 cpu_dump_state(32) error:
> buffer overflow 'env->sregs' 4 <= 255
>
> sregs is declared 'uint32_t sregs[4][16]', so the first index must be
> less than 4.
Hi Stefan,
I think it
I would like to get this into rc1.
> > Feel free to adapt/reorder in any way you see fit to document things.
>
> Ping?
Ack on the part that adds me as maintainer for the virtex board. I'm
assuming this should go via Alex ppc tree.
Acked-by: Edgar E. Iglesias
Cheers,
Edgar
On Fri, Sep 07, 2012 at 04:18:41PM +0200, Aurelien Jarno wrote:
> On Sun, Sep 02, 2012 at 05:33:47PM +, Blue Swirl wrote:
> > Add an explicit CPUState parameter instead of relying on AREG0
> > and switch to AREG0 free mode.
> >
> > Signed-off-by: Blue Swirl
> > ---
> > configure
> > > case 6:
> > >
> > > Similarly to what I reported for the microblaze and sh4 target, I think
> > > we should not start using cpu_single_env (a global variable) to replace
> > > env (a global variable stored in a register).
> > >
> > > It is possible to pass env through the
On Fri, Sep 07, 2012 at 10:36:08PM +0200, Stefan Weil wrote:
> Report from smatch:
>
> target-cris/translate.c:3464 cpu_dump_state(32) error:
> buffer overflow 'env->sregs' 4 <= 255
>
> sregs is declared 'uint32_t sregs[4][16]', so the first index must be
> less than 4 or ARRAY_SIZE(env->sregs).
On Mon, Sep 17, 2012 at 03:36:46PM +0200, Laurent Desnogues wrote:
> On Mon, Sep 17, 2012 at 11:43 AM, Peter Maydell
> wrote:
> > On 17 September 2012 10:30, Laurent Desnogues
> > wrote:
> >> On Mon, Sep 17, 2012 at 1:08 AM, Aurelien Jarno
> >> wrote:
> >>> +#define GEN_SHIFT(name)
On Wed, Sep 19, 2012 at 02:25:48PM +1000, Peter Crosthwaite wrote:
> Ping for PMM,
>
> This is the root case of your block on the SDHCI series - this is a
> discussion on resolution to bogus infinite looping DMA. For current
> participants in this discussion, heres our thread on the same topic
> o
On Wed, Sep 19, 2012 at 10:55:30AM +0300, Avi Kivity wrote:
> On 09/19/2012 07:40 AM, Peter Crosthwaite wrote:
> > On Wed, Sep 19, 2012 at 2:32 PM, Edgar E. Iglesias
> > wrote:
> >> On Wed, Sep 19, 2012 at 02:25:48PM +1000, Peter Crosthwaite wrote:
> >>> Ping f
On Wed, Sep 19, 2012 at 03:12:12PM +0300, Avi Kivity wrote:
> On 09/19/2012 02:46 PM, Edgar E. Iglesias wrote:
> > On Wed, Sep 19, 2012 at 10:55:30AM +0300, Avi Kivity wrote:
> >> On 09/19/2012 07:40 AM, Peter Crosthwaite wrote:
> >> > On Wed, Sep 19, 2012
On Mon, Sep 17, 2012 at 06:47:30PM +1000, Peter A. G. Crosthwaite wrote:
> Misc microblaze patches.
I've applied this (including your indentation fix to patch 5)
Thanks,
Edgar
On Thu, Mar 07, 2013 at 12:11:51PM +1000, Peter Crosthwaite wrote:
> Hi Kuo Jung, Peter,
>
> This patch fixes bugs for us in Zynq Nand (cc Wendy Liang). Can we get
> a cherry pick of this?
I've applied this one.
Thanks,
Edgar
>
> Regards,
> Peter
>
> On Wed, Mar 6, 2013 at 5:27 PM, Kuo-Jung
On Mon, Mar 11, 2013 at 12:17:20PM +0100, Paolo Bonzini wrote:
> The general ideas are (earlier rules override the later, and exceptions
> are of course possible):
>
> - Board files go in hw/ARCH/ (already done).
>
> - Files go in hw/ARCH/ if they reference that arch's CPUState (already done)
>
On Tue, Mar 12, 2013 at 05:53:51PM +0500, Muhammad Nouman wrote:
> Hi ! i am trying to emulate mips on Qemu but at some point the kernel is
> getting a hard interrupt from Qemu which the kernel is not able to understand
> and makes it a spurious interrupt.Can any one tell me that which part of the
On Fri, Aug 16, 2013 at 11:29:44PM -0700, Richard Henderson wrote:
> V2 adds the --adjust-vma idea from Max Filippov.
Thanks Richard, I've applied this
Cheers,
Edgar
>
>
> r~
>
>
> Richard Henderson (3):
> disas: Implement fallback to dump object code as hex
> disas: Add disas-objdump.p
On Wed, Aug 28, 2013 at 08:26:43AM -0700, Richard Henderson wrote:
> On 08/28/2013 07:34 AM, Peter Maydell wrote:
> > On 28 August 2013 15:31, Richard Henderson wrote:
> >> On 08/28/2013 01:15 AM, Peter Maydell wrote:
> >>> [*] not impossible, we already do something on the ppc
> >>> that's simila
On Thu, Sep 25, 2014 at 07:15:29PM +0100, Peter Maydell wrote:
> On 13 September 2014 05:29, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/cpu.h| 19 +++
On Thu, Sep 25, 2014 at 07:39:32PM +0100, Peter Maydell wrote:
> On 13 September 2014 05:29, Edgar E. Iglesias
> wrote:
>
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -3652,7 +3652,33 @@ void switch_mode(CPUARMState *env, int mode)
On Thu, Sep 25, 2014 at 07:47:16PM +0100, Peter Maydell wrote:
> On 13 September 2014 05:29, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/cpu.h | 1 +
> >
On Thu, Sep 25, 2014 at 08:36:41PM +0100, Peter Maydell wrote:
> On 13 September 2014 05:29, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Acked-by: Greg Bellows
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > cpu-e
On Fri, Sep 26, 2014 at 12:01:11AM +0100, Peter Maydell wrote:
> On 25 September 2014 23:20, Edgar E. Iglesias
> wrote:
> > On Thu, Sep 25, 2014 at 07:39:32PM +0100, Peter Maydell wrote:
> >> HCR.TGE isn't actually relevant for some exceptions
> >> (eg SMC),
On Fri, Sep 26, 2014 at 12:17:59AM +0100, Peter Maydell wrote:
> On 25 September 2014 23:55, Edgar E. Iglesias
> wrote:
> > On Thu, Sep 25, 2014 at 07:47:16PM +0100, Peter Maydell wrote:
> >> > +/* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
On Fri, Sep 26, 2014 at 12:43:40AM +0100, Peter Maydell wrote:
> On 26 September 2014 00:31, Edgar E. Iglesias
> wrote:
> > On Fri, Sep 26, 2014 at 12:17:59AM +0100, Peter Maydell wrote:
> >> Oh, yes, that's the trap enable bit. In that case we shouldn't
>
From: "Edgar E. Iglesias"
Hi,
This is a second round of AArch64 EL2/3 patches working on the exception
model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and
Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal
delivery method.
This conflicts sli
From: "Edgar E. Iglesias"
Reviewed-by: Greg Bellows
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 36
target-arm/helper.c | 34 ++
2 files changed, 70 insertions(+)
di
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 19 ++-
target-arm/helper.c | 35 +--
2 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 36507f
From: "Edgar E. Iglesias"
Reviewed-by: Greg Bellows
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c | 5 ++---
target-arm/cpu.h | 15 +++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index bd93165..d017588 100644
--- a/
From: "Edgar E. Iglesias"
Not all exception types update both FAR and ESR.
Reviewed-by: Alex Bennée
Reviewed-by: Greg Bellows
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper-a64.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-arm/help
From: "Edgar E. Iglesias"
Reviewed-by: Alex Bennée
Reviewed-by: Greg Bellows
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a5e8e0d..7f8a410 10
From: "Edgar E. Iglesias"
Reviewed-by: Greg Bellows
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 10 ++
target-arm/helper.c | 17 +
2 files changed, 27 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4070a38..00b3ad4 10
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 1 +
target-arm/helper-a64.c| 1 +
target-arm/helper.c| 20 +++-
target-arm/helper.h| 1 +
target-arm/internals.h | 6 ++
target-arm/op_helper.
From: "Edgar E. Iglesias"
Introduce new_el and new_mode in preparation for future patches
that add support for taking exceptions to and from EL2 and 3.
No functional change.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 7 +++
From: "Edgar E. Iglesias"
This only implements the external delivery method via the GIC.
Acked-by: Greg Bellows
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c | 12
target-arm/cpu.c| 35 ---
target-arm/cpu.h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper-a64.c | 1 +
target-arm/helper.c | 1 +
target-arm/internals.h | 1 +
4 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b553f3
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 1 +
target-arm/helper-a64.c| 1 +
target-arm/helper.c| 3 +++
target-arm/helper.h| 1 +
target-arm/internals.h | 6 ++
target-arm/op_helper.
On Fri, Sep 26, 2014 at 12:43:40AM +0100, Peter Maydell wrote:
> On 26 September 2014 00:31, Edgar E. Iglesias
> wrote:
> > On Fri, Sep 26, 2014 at 12:17:59AM +0100, Peter Maydell wrote:
> >> Oh, yes, that's the trap enable bit. In that case we shouldn't
>
Oops, thanks!
---
Sent from my phone
On Sep 27, 2014 12:46 AM, "Peter Maydell" wrote:
> On 26 September 2014 09:08, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
>
> > static uint64_t
On Tue, Sep 30, 2014 at 04:49:14PM -0500, Greg Bellows wrote:
> From: Fabian Aggeler
>
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions/EL3.
> arm_is_secure_below_el3() returns true if CPU is in secure state
> below EL3.
Hi Greg,
>
>
On Tue, Sep 30, 2014 at 04:49:16PM -0500, Greg Bellows wrote:
> Renamed the arm_current_pl CPU function to more accurately represent that it
> returns the ARMv8 EL rather than ARMv7 PL.
>
> Signed-off-by: Greg Bellows
> ---
> target-arm/cpu.h | 18 +-
> target-arm/helpe
On Tue, Sep 30, 2014 at 04:49:34PM -0500, Greg Bellows wrote:
> From: Fabian Aggeler
>
> Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
> translation functions to use TCR/TTBCR instance depending on CPU state.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
of -d exec has bitten me a couple of times
aswell. A separate patch with an option to disable tb-
chaining would also be helpful imo.
Acked-by: Edgar E. Iglesias
> ---
> I've been burnt at least once by asking a user to do a '-d exec'
> log only to find it didn't actua
rk without
accel=qtest, but maybe that could be an acceptable limitation.
Is there anything in principle with such a setup that would cause problems?
Thanks,
Edgar
commit 947414a56e256139a510a034c02ac277ad577272
Author: Edgar E. Iglesias
Date: Wed Apr 10 20:32:17 2013 +0200
Allow qtest
6 Zeilen entfernt(-)
>
> Ping? Edgar, I haven't seen an ack or nack for this yet. If it's okay
> with you, feel free to apply (rebased version available on my qom-cpu-9
> branch that I could alternatively include in a pull if you prefer).
Sorry for the delay, It lo
On Tue, Apr 16, 2013 at 07:11:43AM +0200, Paolo Bonzini wrote:
> Il 15/04/2013 21:03, Anthony Liguori ha scritto:
> > "Edgar E. Iglesias" writes:
> >
> >> Hi,
> >>
> >> I would like to use qtest for testing hw-models in combination with
On Tue, Apr 16, 2013 at 10:18:08AM +1000, peter.crosthwa...@xilinx.com wrote:
> From: Peter Crosthwaite
>
> Hi all. The Xilinx AXIEnet and DMA devices have two AXI stream connections
> (control and data), only one of which is currently modelled (data). AXI stream
> is modelled using the stream QO
On Tue, Apr 16, 2013 at 10:32:14AM +1000, peter.crosthwa...@xilinx.com wrote:
> From: Peter Crosthwaite
>
> Fix up the debug printfery m25p80 in various ways. 0 functional diff.
>
> changed from v2:
> Rebased against hw reorg
Applied, thanks!
Cheers,
Edgar
>
>
> Peter Crosthwaite (4):
> m
On Wed, Apr 17, 2013 at 03:04:48PM +0200, Andreas Färber wrote:
> Hi,
>
> Am 17.04.2013 11:21, schrieb Moese, Michael:
> >> I think your best bet is to ask GreenSocs if you need support for this
> >> codebase.
> >
> > I think you'd be right when you point me to GreenSocs, but.. they don't
> > s
ase against recent configure devls.
> changed since v2:
> Fixed P1 implementation (PMM review)
> Fixed CC/AR/LD quoting issue P3 (PMM review)
> Addressed PMM review
> changed since v1:
> Fixed cross compilation of submodules (new P1)
> Fixed passing of ARFLAGS to dtc submake
A
On Thu, Apr 18, 2013 at 01:02:41PM +0200, Paolo Bonzini wrote:
> Il 18/04/2013 12:26, Edgar E. Iglesias ha scritto:
> > On Thu, Apr 18, 2013 at 02:45:35PM +1000, peter.crosthwa...@xilinx.com
> > wrote:
> >> From: Peter Crosthwaite
> >>
> >> These two pat
On Thu, Apr 18, 2013 at 02:45:35PM +1000, peter.crosthwa...@xilinx.com wrote:
> From: Peter Crosthwaite
>
> These two patches add and use dtc as a submodule as per the RFC:
>
> http://lists.gnu.org/archive/html/qemu-devel/2013-01/msg05000.html
>
> There is a remaining action item to mandate lib
On Thu, Apr 18, 2013 at 12:10:54PM +0100, Peter Maydell wrote:
> On 18 April 2013 12:08, Edgar E. Iglesias wrote:
> > On Thu, Apr 18, 2013 at 01:02:41PM +0200, Paolo Bonzini wrote:
> >> For submodules that do have autoconf-generated scripts in the repository
> >> (I th
On Wed, Apr 17, 2013 at 04:26:34PM +0200, Paolo Bonzini wrote:
> This series expands on the one I sent yesterday, but also fixes some
> confusion between target (CPU) and ABI types in linux-user/elfload.c.
>
> target_short/int/llong and the corresponding unsigned types are renamed
> to abi_short/i
On Mon, Apr 22, 2013 at 02:40:09PM +1000, peter.crosthwa...@xilinx.com wrote:
> From: Peter Crosthwaite
>
> Two issues reported by Blue for building the DTC submodule with clang
> and mingw.
Applied
Fixes the mingw build on my setup, thanks.
Cheers,
Edgar
>
>
> Peter Crosthwaite (2):
> Ma
On Fri, Apr 26, 2013 at 01:48:45PM +0200, Andreas Färber wrote:
> Hi,
>
> Am 24.04.2013 13:31, schrieb edgar.igles...@gmail.com:
> > From: "Edgar E. Iglesias"
> >
> > Configurable at CPU synthesis/instantiation.
> >
> > Signed-off-by: Edga
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 90a946a..25ad902 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/o
From: "Edgar E. Iglesias"
Break out code to save/restore AArch64 SP into functions.
Signed-off-by: Edgar E. Iglesias
---
target-arm/internals.h | 29 -
target-arm/kvm64.c | 13 +++--
target-arm/op_helper.c | 6 +-
3 files changed, 24
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2ee3da2..5114d26 100644
--- a/target-arm/cpu.h
+++ b/
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 35 +++
target-arm/helper.c | 27 +++
2 files changed, 62 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5114d26..cd8c
From: "Edgar E. Iglesias"
Introduce new_el and new_mode in preparation for future patches
that add support for taking exceptions to and from EL2 and 3.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 7 +++
target-arm/helper-
From: "Edgar E. Iglesias"
Hi,
This is a second round of AArch64 EL2/3 patches working on the exception
model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and
Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal
delivery method.
Patch 3 is a bug fix
From: "Edgar E. Iglesias"
Reviewed-by: Alex Bennée
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2f262a5..6aed57c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper-a64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index cccda74..bc153cb 100644
--- a/target-arm/helper-a64.c
+++ b/target-
From: "Edgar E. Iglesias"
No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.c| 2 +-
target-arm/cpu.h| 2 +-
target-arm/helper-a64.c | 4 ++--
target-arm/helper.
From: "Edgar E. Iglesias"
Avoids the explicit 16bit mask. No functional change.
Signed-off-by: Edgar E. Iglesias
---
target-arm/internals.h | 14 +++---
target-arm/translate-a64.c | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/int
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