Oops, thanks!
---
Sent from my phone
On Sep 27, 2014 12:46 AM, "Peter Maydell" <peter.mayd...@linaro.org> wrote:
> On 26 September 2014 09:08, Edgar E. Iglesias <edgar.igles...@gmail.com>
> wrote:
> > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
>
> > static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> > {
> > ARMCPU *cpu = arm_env_get_cpu(env);
> > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
> > .resetvalue = 0 },
> > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.c1_scr),
> > - .resetvalue = 0, },
> > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.scr_el3),
> > + .resetvalue = 0, .writefn = scr_write },
> > { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
> > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
> > .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE
> },
> > @@ -2314,6 +2340,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
> > .access = PL3_RW, .writefn = vbar_write,
> > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
> > .resetvalue = 0 },
> > + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
> > + .type = ARM_CP_NO_MIGRATE,
> > + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
> > + .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
> cp15.scr_el3),
> > + .writefn = scr_write },
> > REGINFO_SENTINEL
> > };
>
> You've applied the "offsetoflow32" to the wrong reginfo:
> it goes on the one for the 32 bit reg, not the one for
> the 64 bit reg.
>
> Since this is a trivial thing I'm going to just fix it
> up as I put this patch into target-arm.next. (I don't
> know yet if I can put the whole series in but I'm
> planning to put at least the start of it in.)
>
> thanks
> -- PMM
>
