XXX This patch needs double checking... It fixed 32-bit userspace
but I'm not sure it's right. I wonder whether msr_is_64bit() should
be applied to env->msr, not msr, but I need to double check the
architecture.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/excp_helper.c | 4
We don't use the resulting accessors and this gets in the way of
the split I/D TLB work.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b34aed6..9ef0859 100644
--- a/target-ppc/
Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
are offset by that value in order to preserve consistency with the
HW implementations.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu-qom.h| 1 +
target-ppc/translate_init.c | 8 +++-
2 files changed, 8
t the
hypervisor callback to be the same as the supervisor one. The new
registration function only needs to be used for registers that are
either hypervisor only or behave differently in HV mode.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 26 +
Otherwise it will trip on the forms used in recent architecture.
Ideally, we should have different handlers for different architecture
levels but our current implementation of TLB flushing is dumb enough
that this will do for now.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc
This will enable decoding of hrfid
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 76f20ea..f11e7d0 100644
--- a/target-ppc
We rework the way the MMU indices are calculated, providing separate
indices for I and D side based on MSR:IR and MSR:DR respectively,
and thus no longer need to flush the TLB on context changes. This also
adds correct support for HV as a separate address space.
Signed-off-by: Benjamin
None of the other presenter functions directly mucks with the
internal state, so don't do it there either.
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c| 8
hw/intc/xics_spapr.c | 7 ---
include/hw/ppc/xics.h | 1 +
3 files changed, 13 insertions(+), 3 dele
select
the right exception type and registers. On pre-P7 processors, LPCR
is 0 which provides the old behaviour of directing the interrupts
at the supervisor.
Thanks to Andrei Warkentin for finding a bug when HV=1
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mmu-hash64.c | 66
This adds the ISA 2.06 and later power management instructions
(doze, nap, sleep and rvwinkle) and associated wakeup cause testing
in LPCR
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 26 -
target-ppc/excp_helper.c| 59
And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/spapr.c
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c| 6 ++
hw/intc/xics_spapr.c | 3 +--
include/hw/ppc/xics.h | 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 0c355f4..3cd696f 100644
--- a/hw/intc/xics.c
+++ b/hw/intc
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c| 11 ---
include/hw/ppc/xics.h | 1 -
2 files changed, 12 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 165ff0b..197df33 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -678,17 +678,6 @@ void
Properly implement LPES0/1 handling for HV vs. !HV mode and fix AIL
implementation.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 2 +
target-ppc/excp_helper.c| 175 ++--
target-ppc/translate_init.c | 2 +-
3 files
Not that anything remotely recent supports tlbia but ...
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 10eb9e3..014fe5e 100644
--- a/target-ppc
nical replacement of all those instances to use the name
"xics" instead. There should be no functional change.
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c | 132 ++--
hw/intc/xics_kvm.c | 54 +
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 39 +++
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4d01fd0..a5ab2eb 100644
--- a/target-ppc/translate.c
+++ b/target
We were initializing unused ones and missing some
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 11 ++-
target-ppc/translate_init.c | 27 +--
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc
everywhere.
This reworks it all, using little helper macros for checking, and
adding the HV interrupt (which gets converted back to program check
in the slow path of excp_helper.c on CPUs that don't want it).
Signed-off-by: Benjamin Herrenschmidt
---
linux-user/main.c| 1 +
targe
this function and its callers to work this way.
>
> As a bonus, this slightly simplifies the emulation of segment
> registers for
> when running a 32-bit OS on a 64-bit CPU.
>
> Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
> ---
> target-ppc/kvm.c|
ts to just a deposit64(), so remove
> it and
> have the callers use deposit64() directly.
>
> Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
> ---
> target-ppc/cpu.h| 1 +
> target-ppc/machine.c| 20 +
> target-ppc/mmu-h
hpte_page_shift()
> function which looks up the page size of an HPTE. We use this to
> validate
> page sizes encodings on faults, and populate the qemu TLB with larger
> page sizes when appropriate.
>
> Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
(Note
ifferent places, and do different things.
>
> Clean this up by separating out the tlbiva instruction into its own
> handling. In fact the implementation is only a stub anyway.
>
> Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
> ---
> target-ppc/helper.
fers and
tlbie does provide additional information on server processors that
we would need should we chose to implemented fine grained invalidations
(such as the page size).
In the meantime:
Acked-by: Benjamin Herrenschmidt
> Signed-off-by: David Gibson
> ---
> target-ppc/mmu_help
rly ? IE, tlbie will give us the page size using the same encoding
as the HPTE iirc when L=1 ? To be honest the encoding of tlbie in arch
2.07 is so completely insane I have a hard time figuring it out myself
... :-)
Otherwise,
Acked-by: Benjamin Herrenschmidt
> Signed-off-by: David Gibso
ans that the spapr code should now be able to handle any page
> size
> listed in the env->sps table.
>
> Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
> ---
> hw/ppc/spapr_hcall.c| 25 ++---
> target-ppc/mmu-hash64.c | 35 ++
previously
> didn't support in TCG.
>
> Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
> ---
> target-ppc/mmu-hash64.h | 2 ++
> target-ppc/translate_init.c | 32
> 2 files changed, 34 insertions(+)
>
>
This allows a bus class to tell whether a given bus has room for
any new device. max_dev isn't sufficient as the rules can depend
on some arguments or can differ between instances of a bus. This
will be used by PCI in subsequent patches
Signed-off-by: Benjamin Herrenschmidt
---
include/hw
No devices yet, not even an interrupt controller, just to get
started.
Signed-off-by: Benjamin Herrenschmidt
---
default-configs/ppc64-softmmu.mak | 1 +
hw/ppc/Makefile.objs | 2 +
hw/ppc/pnv.c | 600 ++
include/hw/ppc
The common class doesn't change, the KVM one is SPAPR specific, this
is a preliminary change to make it easier to support "native" XICS.
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c| 26 +-
hw/intc/xics_kvm.c| 6 +++---
hw/ppc/spap
It will not be used by the native implementation. This allows us to
also remove the include of spapr.h from the common code
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c| 12
hw/intc/xics_kvm.c| 13 -
hw/intc/xics_spapr.c | 13
esent in the Naples version
of the chip though some preliminary work is there.
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/pnv.c | 49 -
hw/ppc/pnv_lpc.c | 527 +++
include/hw/ppc/pnv.h | 5 +
4
Instead of an array of fixed sized blocks, use a list, as we will need
to have sources with variable number of interrupts. SPAPR only uses
a single entry. Native will create more. If performance becomes an
issue we can add some hashed lookup but for now this will do fine.
Signed-off-by: Benjamin
Leave the core ICP/ICS logic in xics.c and move the top level
class wrapper, hypercall and RTAS handlers to xics_spapr.c
Signed-off-by: Benjamin Herrenschmidt
---
default-configs/ppc64-softmmu.mak | 1 +
hw/intc/Makefile.objs | 1 +
hw/intc/xics.c| 390
Otherwise QEMU might add a device at slot 0 which isn't supported
by the SHPC controller.
Signed-off-by: Benjamin Herrenschmidt
---
hw/pci-bridge/pci_bridge_dev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
index 26
Useful to debug interrupt problems.
Signed-off-by: Benjamin Herrenschmidt
---
hmp-commands-info.hx | 2 ++
hw/intc/xics.c| 38 ++
hw/ppc/ppc.c | 14 ++
include/hw/ppc/ppc.h | 2 ++
include/hw/ppc/xics.h | 2 ++
monitor.c
y the surrounding hardware that we do need, which is the
interrupt generation facility. OPAL uses it to send itself interrupts
under some circumstances and there are other uses around the corner.
So this implement just enough to support this.
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/Makefile
is accessed.
This provides a simple bus and device type for devices sitting on
XSCOM along with some facilities to optionally generate corresponding
device-tree nodes
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/pnv.c | 11 ++
hw/ppc
This provides MMIO based ICP access as found on POWER8
Signed-off-by: Benjamin Herrenschmidt
---
default-configs/ppc64-softmmu.mak | 3 +-
hw/intc/Makefile.objs | 1 +
hw/intc/xics_native.c | 294 ++
include/hw/ppc/xics.h
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/mmu-hash32.c | 4 ++--
target-ppc/mmu_helper.c | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index dfee358..a2f4ce2 100644
--- a/target-ppc/mmu-hash32.c
+++ b
This is currently missing on both PowerNV and PAPR
FIXME: Split patch & fix tabs
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/pnv.c| 8
target-ppc/translate_init.c | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 179
This will make life easier for dealing with dynamically configured
ICSes such as PHB3
Signed-off-by: Benjamin Herrenschmidt
---
include/hw/ppc/xics.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 12fc584..51a63cb 100644
Make sure we give the guest full authorization
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f3f6cf5..df24b97 100644
--- a/target-ppc/translate_init.c
t child to avoid having qemu put dumb devices at different
slot numbers.
Signed-off-by: Benjamin Herrenschmidt
---
hw/pci/pci.c | 22 ++
include/hw/pci/pci_bus.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 168b9cc..7003
With appropriate AMR-like masks. Not actually used by the translation
logic at that point
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 40 +++-
2 files changed, 40 insertions(+), 1 deletion
we don't try to use 64K pages on 970.
This still doesn't add support for MPSS (Multiple Page Sizes per Segment)
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/spapr_hcall.c| 10 +++--
target-ppc/cpu.h| 7 --
target-ppc/mm
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/pnv.c | 69 +++
include/hw/ppc/pnv.h | 2 ++
include/hw/ppc/xics.h | 2 ++
3 files changed, 73 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2eac877..a7a9b0f 100644
--- a
x27;t seem like a terribly good idea.
Signed-off-by: Benjamin Herrenschmidt
---
hw/pci/pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 7003f7c..b364eff 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1298,7 +1298,9 @@ qemu_irq p
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 7 +++
target-ppc/translate_init.c | 28
2 files changed, 35 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 756a66f..f7e653b 100644
--- a/target-ppc/cpu.h
+++ b/target
This adds just enough of the PSI bridge to handle various on-chip
and the one external interrupt. The rest of PSI has to do with
the link to the IBM FSP service processor which we don't plan to
emulate (not used on OpenPower machines).
Signed-off-by: Benjamin Herrenschmidt
---
h
Those are HV writeable, so we provide a dummy write. We eventually need
to provide a better emulation but for now this will get us going.
We also make them non-user readable as per the architecture.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c | 24
This handles filtering bits based on what is implemented by a
given architecture version. We also use it to copy to LPCR
some of the relevant 970 HID4 bits.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/helper.h | 1 +
target-ppc/mmu-hash64.c | 58
The Hypervisor can write it. We don't handle that properly yet but
at least let's not blow up when it is written.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/
Includes all the bits up to ISA 2.07
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a7236cf..ca6c961 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
It's supposed to be an instruction counter. For now make us not
crash when accessing it.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 12
2 files changed, 13 insertions(+)
diff --git a/target-ppc/cpu.h b/targe
WORT and PID this time
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 2 ++
target-ppc/translate_init.c | 16
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index aa328a7..6179fbc 100644
--- a/target
The architecture specifies that any instruction that sets MSR:PR will also
set MSR:EE, IR and DR.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/helper_regs.h | 4
1 file changed, 4 insertions(+)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 12af61c..09bc450
orm.
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/pnv.c | 99 +++-
1 file changed, 98 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d808802..179f93b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -52,6 +5
Controls the micropartition prefetch, this is pretty much meaningless
in full emulation (used for priming the caches on real HW).
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 13 +
2 files changed, 14 insertions(+)
diff
Don't allow access in guest mode
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bfc7a6d..e3887e7 100644
--- a/targe
limit to the max supported by the
implementation (16G).
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/spapr.c | 7 +++
target-ppc/mmu-hash64.c | 146 ++--
target-ppc/mmu-hash64.h | 1 +
target-ppc/translate_init.c | 10 ++-
4
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 4
2 files changed, 5 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index bf8892a..aa328a7 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1361,6 +1361,7
The masks weren't chosen nor applied properly. The architecture specifies
that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0.
The writes to UAMOR are masked by AMOR for HV=0
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c
External interrupts can bypass the MSR_EE test if they occur in guest
mode and LPES0 is clear. In that case they are directed to the hypervisor
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/excp_helper.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate_init.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bfdf028..fd084ca 100644
--- a/target-ppc/translate_init.c
+++ b
The current behaviour isn't completely right, as for the DEC, we
don't properly re-arm when wrapping around, but I will fix this
in a separate patch.
Signed-off-by: Benjamin Herrenschmidt
---
hw/ppc/ppc.c | 17 -
target-ppc/excp_helper.
On real hardware it allows temporary thread priority boosts, we don't
do threads and implementing it would be fairly tricky, so we just dummy
it or now.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 11 +++
2 files ch
We still need to eventually implement doorbells but at least this
makes us not crash when the SPRs are accessed.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 2 ++
target-ppc/translate_init.c | 17 +
2 files changed, 19 insertions(+)
diff --git a
Used to lookup SLB entries by address, for some reason it was missing.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/helper.h | 1 +
target-ppc/mmu-hash64.c | 24
target-ppc/translate.c | 25 +
3 files changed, 50 insertions(+)
diff
We need to remove 4 from the NIP since it's already been moved by
4 by the dispatcher before the helper is called
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate.c b/targe
On Wed, 2015-11-11 at 11:27 +1100, Benjamin Herrenschmidt wrote:
> This requires an OPAL firmware file which isn't included yet,
> will emulate enough to boot existing distros and run KVM
> inside TCG
Note that this doesn't migrate nor supports running under PR KVM,
both ar
We should implement HW breakpoint/watchpoint, qemu supports them...
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 334fcfe..bf8892a
They are generally useful when debugging HV mode stuff
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f76a0c3..b34d2c6 100644
--- a/target-ppc/translate.c
+++ b
On Tue, 2015-11-10 at 17:50 -0700, Eric Blake wrote:
>
> It would be nice to include a diffstat (git defaults to doing this if
> you use 'git format-patch --cover-letter' for generating the 0/77
> letter), so that we can see at a glance how big this series is and
> what files it touches.
Right. I
It's used by KVM for micropartition prefetch
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b34d2c6..1e3996d 100644
--- a/target-ppc/translate.c
There's no point inlining this, if you hit the exception case you exit
anyway, and not inlining saves about 100K of code size (and cache
footprint).
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --
Otherwise tight loops at smt_low for example, which OPAL does,
eat so much CPU that we can't boot a kernel anymore. With that,
I can boot 8 CPUs just fine with powernv.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 19 +--
1 file changed, 17 insertions(
This helper is only used by the various instructions that can alter
MSR and not interrupts. Add a comment to that effect to the interrupt
code as well in case somebody wants to change this
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/excp_helper.c | 8 ++--
target-ppc/helper_regs.h
From: Michael Neuling
Signed-off-by: Michael Neuling
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bd5df40..3974cd2 100644
--- a/target-ppc
Those instructions are only available in hypervisor real mode and
allow cache inhibited garded access to devices in that mode.
Signed-off-by: Benjamin Herrenschmidt
---
target-ppc/cpu.h| 4 +++-
target-ppc/translate.c | 56 +++--
target
ned-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c| 123 --
hw/intc/xics_kvm.c| 2 +-
hw/intc/xics_spapr.c | 34 --
include/hw/ppc/xics.h | 12 +++--
4 files changed, 108 insertions(+), 63 deletions(-)
diff --git a/hw/i
This is a model of the PCIe host bridge found on Power8 chips,
including IOMMU support, PCIe root complex etc...
This implementation doesn't emulate the EEH error handling (and
may never do).
Signed-off-by: Benjamin Herrenschmidt
---
hw/intc/xics.c |2 +-
hw/pci
On Wed, 2015-11-11 at 14:27 +1100, Alexey Kardashevskiy wrote:
> On 11/11/2015 11:56 AM, Benjamin Herrenschmidt wrote:
> > On Tue, 2015-11-10 at 17:50 -0700, Eric Blake wrote:
> > >
> > > It would be nice to include a diffstat (git defaults to doing
> > > thi
On Wed, 2015-11-11 at 15:07 +1100, Alexey Kardashevskiy wrote:
>
> p/qemu-powernv/ppc64-softmmu/qemu-system-ppc64 -m 2048 -machine
> powernv \
> -nographic -vga none -initrd t/le.cpio -kernel t/vml420le -bios \
> skiboot.lid -smp 1,threads=1
>
> just hangs at:
>
> [1491287872,5] INIT: Waiting fo
On Wed, 2015-11-11 at 15:41 +1100, Alexey Kardashevskiy wrote:
> Another note. I tried to know what the default devices are and got
> another
> crash:
>
> (qemu) info qtree
> bus: main-system-bus
> type System
> dev: phb3-msi, id ""
> /home/aik/p/qemu-powernv/hw/core/sysbus.c:276:sysbus_dev
On Thu, 2015-11-12 at 13:02 -0600, miny...@acm.org wrote:
> This is a long delayed patch set, but I think I have things reworked
> to make Igor happy with the way ACPI and SMBIOS work. This is more
> consistent with the way most other things work, anyway. It did
> require adding stubs for systems
On Mon, 2015-11-16 at 16:34 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:26AM +1100, Benjamin Herrenschmidt
> wrote:
> > Not that anything remotely recent supports tlbia but ...
> >
> > Signed-off-by: Benjamin Herrenschmidt
> > ---
> > target-pp
Thanks for reviewing !
On Mon, 2015-11-16 at 15:49 +1100, David Gibson wrote:
> > static inline void hreg_compute_mem_idx(CPUPPCState *env)
> > {
> > -/* Precompute MMU index */
> > -if (msr_pr == 0 && msr_hv != 0) {
> > -env->mmu_idx = 2;
> > +/* This is our encoding for ser
On Mon, 2015-11-16 at 16:01 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:17AM +1100, Benjamin Herrenschmidt wrote:
> > We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
> > so let's use these versions, without that some firmware or Linux code
&
On Mon, 2015-11-16 at 16:00 +1100, David Gibson wrote:
>
> > //#define DEBUG_MMU
> > //#define DEBUG_BATS
> > @@ -1940,6 +1941,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> > case POWERPC_MMU_2_03:
> > case POWERPC_MMU_2_06:
> > case POWERPC_MMU_2_07:
> > +env->tlb_
On Tue, 2015-11-17 at 11:32 +1100, Alexey Kardashevskiy wrote:
> On 11/11/2015 11:27 AM, Benjamin Herrenschmidt wrote:
> > This adds a model of the POWER8 LPC controller. It is then used
> > by the PowerNV code to attach a UART and RTC, which, with the right
> > version o
On Tue, 2015-11-17 at 11:11 +1100, Alexey Kardashevskiy wrote:
>
> I have never heard of anyone testing migration of TCG guests. KVM guests
> use host PVR anyway.
>
> I just wonder that we "never released anything older than" but we still
> support them in the kernel - why do not we wipe these
On Mon, 2015-11-16 at 21:21 +1100, Benjamin Herrenschmidt wrote:
>
> Ah you are right. I do have second thoughts about that previous patch
> now that you mention it however. In the real MSR, HV and PR are
> independant, I wonder if I'm better off making the check explicit...
>
On Wed, 2015-11-18 at 13:34 +0100, Paolo Bonzini wrote:
../..
> Tabs for indentation. There are other occurrences in the patch.
Ooops. sorry, missed those. Do you need a respin ?
> Apart from this,
>
> Reviewed-by: Paolo Bonzini
> Acked-by: Paolo Bonzini
>
> > if (ret && !qbu
On Thu, 2015-11-19 at 17:11 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:20AM +1100, Benjamin Herrenschmidt
> wrote:
> > We don't give them a KVM reg number yet as no current KVM version
> > supports HV mode.
> >
> > Signed-off-by: Benjamin Herre
On Thu, 2015-11-19 at 17:19 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:22AM +1100, Benjamin Herrenschmidt
> wrote:
> > XXX This patch needs double checking... It fixed 32-bit userspace
> > but I'm not sure it's right. I wonder whether msr_is_64bit()
On Thu, 2015-11-19 at 17:26 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:28AM +1100, Benjamin Herrenschmidt
> wrote:
> > From: Michael Neuling
> >
> > Signed-off-by: Michael Neuling
> > Signed-off-by: Benjamin Herrenschmidt
>
> Reviewed-
On Thu, 2015-11-19 at 17:44 +1100, David Gibson wrote:
>
> > -/* new interrupt handler msr */
> > -new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> > +/* new interrupt handler msr preserves existing HV and ME unless
> > + * explicitly overriden
> > + */
> > +new_msr = en
On Thu, 2015-11-19 at 21:23 +1100, Benjamin Herrenschmidt wrote:
>
> I only just discovered that rfi is actually gone from arch 2.07 :-)
>
> I'll dig a bit more tomorrow.
Ok, so I had a closer look and tore that stuff appart even more :-)
If you are curious, feel free to check
On Mon, 2015-11-16 at 16:16 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:21AM +1100, Benjamin Herrenschmidt
> wrote:
> > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
> > are offset by that value in order to preserve consistency with the
>
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