ore is not
the one used by softfloat.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-4-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/ta
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_he
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8
tests/tcg/tricore/asm/macros.h | 9 +
tests/tcg/tricore/asm/test_insert.S | 5 +
3
as this is an effective address and those cannot be signed,
it should not be a signed integer.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-11-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16
1 file changed, 8 insertions
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 32 +++
target/tricore/helper.h | 1 +
target/tricore/trans
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-10-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++
1 file
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann
Message-ID: <20230913105326.40832-2-kbast...@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/ma
this is not something other ISAs do, so clarify it with a comment.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 5 +
1 file changed, 5 insertions(+)
diff -
Reviewed-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann
Message-ID: <20230828112651.522058-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 36 +++
target/tricore/he
ranslate.c
> index 1947733870..6ae5ccbf72 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On Wed, Aug 09, 2023 at 10:29:44AM +0200, Paolo Bonzini wrote:
> The tricore tools are not detected when they are installed in
> the host system, only if they are taken from an external
> container. For this reason the build-tricore-softmmu job
> was not running the TCG tests.
>
> In addition the
On Wed, Aug 09, 2023 at 03:49:01PM +0200, Bastian Koppelmann wrote:
> On Wed, Aug 09, 2023 at 10:29:44AM +0200, Paolo Bonzini wrote:
> > The tricore tools are not detected when they are installed in
> > the host system, only if they are taken from an external
> > container.
On Wed, Aug 09, 2023 at 10:29:45AM +0200, Paolo Bonzini wrote:
> With the release of version 12 on June 10, 2023, Debian 10 is
> not supported anymore. Modify the cross compiler container to
> build on a newer version.
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/docker/dockerfiles/debian-tri
On Wed, Aug 09, 2023 at 04:33:37PM +0200, Paolo Bonzini wrote:
> On Wed, Aug 9, 2023 at 3:53 PM Bastian Koppelmann
> wrote:
> > > diff --git a/tests/docker/dockerfiles/debian-tricore-cross.docker
> > > b/tests/docker/dockerfiles/debian-tricore-cross.docker
> > &g
Hi Rui,
On Thu, Jul 06, 2023 at 12:59:55PM -0400, Rui Chen wrote:
> While upgrading capstone to v5, there was some name clash with the
> tricore_feature in capstone (which was introduced in this PR), thus rename
> tricore_feature to is_tricore_feature_enabled.
>
> Build error log is below
>
> /o
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c | 10 +-
target/tricore/translate.c | 12 ++--
target/tricore/tricore-opcodes.h | 3 ++-
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 8
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
4 files changed, 17 insertions(+)
diff --git a/target/tricore/helper.h b/target
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 14 --
target/tricore/tricore-opcodes.h | 9 -
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 26b284bcec..898557d22a 100644
we also introduce the tc37x CPU that implements that ISA version.
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.c | 13 +
target/tricore/cpu.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 7fa113fed2..f15169bd1b
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cd33a1dcdd..26b284bcec 100644
--- a/target/tricore/translate.c
/-/issues/1667
Bastian Koppelmann (6):
target/tricore: Introduce ISA 1.6.2 feature
target/tricore: Add popcnt.w insn
target/tricore: Add LHA insn
target/tricore: Add crc32l.w insn
target/tricore: Add crc32.b insn
target/tricore: Add shuffle insn
target/tricore/cpu.c | 13
this is mostly authored by volumit (https://github.com/volumit/qemu/)
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 48
target/tricore/translate.c | 8 ++
target/tricore/tricore
all bytes in parallel
Bastian Koppelmann (6):
target/tricore: Introduce ISA 1.6.2 feature
target/tricore: Add popcnt.w insn
target/tricore: Add LHA insn
target/tricore: Add crc32l.w insn
target/tricore: Add crc32.b insn
target/tricore: Add shuffle insn
target/tricore/cpu.c |
this is based on code by volumit (https://github.com/volumit/qemu/)
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Shuffle now uses shifts, instead of a buffer
- Shuffle now does rev8 for all bytes in parallel
target/tricore/helper.h | 1 +
target/tricore/op_helpe
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 8
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
4 files changed, 17 insertions(+)
diff --git a
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c | 10 +-
target/tricore/translate.c | 12 ++--
target/tricore/tricore-opcodes.h | 3 ++-
4 files changed, 23 insertions(+), 5
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cd33a1dcdd..26b284bcec 100644
we also introduce the tc37x CPU that implements that ISA version.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.c | 13 +
target/tricore/cpu.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 14 --
target/tricore/tricore-opcodes.h | 9 -
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
emu-project/qemu/-/issues/1698
> Reported-by: Siqi Chen
> Signed-off-by: Siqi Chen
> ---
> target/tricore/translate.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
From: Siqi Chen
When translating "imask" instruction of Tricore architecture, QEMU did not
check whether the register index was out of bounds, resulting in a
global-buffer-overflow.
Reviewed-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698
R
some insns were not checking if an even index was used to access a 64
bit register. In the worst case that could lead to a buffer overflow as
reported in https://gitlab.com/qemu-project/qemu/-/issues/1698.
Reported-by: Siqi Chen
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c
tps://gitlab.com/qemu-project/qemu/-/issues/1700
Signed-off-by: Bastian Koppelmann
---
target/tricore/op_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index d3c836ecd9..cbc46b2a5f 100644
--- a/target/tric
we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699
Signed-off-by: Bastian Koppelmann
---
target/tricore/op_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/tricore/op_hel
Hi,
this series fixes a bunch of TriCore issues on the bugtracker.
Cheers,
Bastian
Bastian Koppelmann (3):
target/tricore: Correctly fix saving PSW.CDE to CSA on call
target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs
target/tricore: Fix helper_ret() not correctly
d-by: Richard Henderson
> ---
> target/tricore/helper.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cd33a1dcdd..26b284bcec 100644
all bytes in parallel
v2 -> v3:
- Added patch to implement SYSCALL (resolves
https://gitlab.com/qemu-project/qemu/-/issues/1452)
- Added patch to implement DISABLE insn variant
Bastian Koppelmann (8):
target/tricore: Introduce ISA 1.6.2 feature
target/tricore: Add popcnt.w insn
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 14 --
target/tricore/tricore-opcodes.h | 9 -
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 11 ++-
ta
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a4c60e8ae2..f01000efd4 100644
--- a
we also introduce the tc37x CPU that implements that ISA version.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.c | 13 +
target/tricore/cpu.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c | 10 +-
target/tricore/translate.c | 12 ++--
target/tricore/tricore-opcodes.h | 3 ++-
4 files changed, 23 insertions(+), 5
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 8
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
4 files changed, 17 insertions(+)
diff --git a
this is based on code by volumit (https://github.com/volumit/qemu/)
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 36
target/tricore/translate.c | 8 +++
target/tricore/tricore
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 41 +-
1 file changed, 32 insertions(+), 9 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a0644dd120..edbc319fa1 100644
--- a/target/tricore
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.h | 17 -
target/tricore/translate.c | 15 +--
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 041fc0b6e5..257fcf3cee 100644
--- a/target
ned-off-by: Bastian Koppelmann
---
target/tricore/op_helper.c | 11 +++
target/tricore/translate.c | 2 ++
2 files changed, 13 insertions(+)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 026e15f3e0..17b78c501c 100644
--- a/target/tricore/op_helper.c
++
bit. So I fixed that as well.
Cheers,
Bastian
Bastian Koppelmann (4):
target/tricore: Introduce priv tb flag
target/tricore: Implement privilege level for all insns
target/tricore: Honour privilege changes on PSW write
target/tricore: Fix ICR.IE offset in RESTORE insn
target/tricore
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/tric
On Thu, Jun 15, 2023 at 09:37:23AM +0200, Richard Henderson wrote:
> On 6/14/23 18:59, Bastian Koppelmann wrote:
> > void helper_psw_write(CPUTriCoreState *env, uint32_t arg)
> > {
> > +uint32_t old_priv, new_priv;
> > +CPUState *cs;
> > +
> > +
On Thu, Jun 15, 2023 at 05:15:28PM +0200, Bastian Koppelmann wrote:
> On Thu, Jun 15, 2023 at 09:37:23AM +0200, Richard Henderson wrote:
> > On 6/14/23 18:59, Bastian Koppelmann wrote:
> > > void helper_psw_write(CPUTriCoreState *env, uint32_t arg)
> > > {
&
this replaces all calls to tcg_gen_exit_tb() and moves them to
tricore_tb_stop().
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore
to main-loop | PATCH [03/08]
- Indirect jumps us tcg_gen_lookup_and_goto_ptr() | PATCH [04/08]
- Removed (uint32_t) cast | PATCH [05/08]
- Removed psw_write() calling cpu_loop_exit() | PATCH [07/08]
Bastian Koppelmann (8):
target/tricore: Fix RR_
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 47 --
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 44f1c1022f..71e3842601
ned-off-by: Bastian Koppelmann
---
v1 -> v2:
- Removed helper_psw_write() calling cpu_loop_exit().
Instead we unconditionally exit for each write to psw.
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/t
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Removed (uint32_t) cast
target/tricore/cpu.h | 17 -
target/tricore/translate.c | 14 --
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/target/tricore/cp
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
if A[r1] == A[11], then we would overwrite the destination address of
the jump with the return address.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c
so we can recognize exceptions after re-enabling interrupts.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d4f7415158
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6164ba6539..5515dfa3f3 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
this replaces all calls to tcg_gen_exit_tb() and moves them to
tricore_tb_stop().
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/tricore
if A[r1] == A[11], then we would overwrite the destination address of
the jump with the return address.
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.h | 17 -
target/tricore/translate.c | 14 --
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 041fc0b6e5
end the TB | PATCH [03/08]
- generate_trap() for indirct jump now set | PATCH [04/08]
DISAS_NORETURN |
Bastian Koppelmann (8):
target/tricore: Fix RR_JLI clobbering reg A[11]
target/tricore: Introduce DISAS_TARGET_EXIT
target/tric
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 43 +-
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1a0c6d35d3..1d570b49ff
eviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1d570b49ff..71b6209af4 100644
--- a/target/tricore/translate.c
+++ b/targ
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- generate_trap() for indirct jump now set DISAS_NORETURN
target/tricore/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 025b12567a..3d0c90b
so we can recognize exceptions after re-enabling interrupts.
Reviewed-by: Richard Henderson
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- DISABLE insns don't end the TB
target/tricore/translate.c | 5 +
1 file changed, 5 insertions(+)
diff
On Wed, Jun 21, 2023 at 01:06:33PM +0200, Richard Henderson wrote:
> On 6/21/23 12:19, Bastian Koppelmann wrote:
> > from ISA v1.6.1 onwards the bit position of ICR.IE changed.
> > ctx->icr_ie_offset contains the correct value for the ISA version used
> > by the vCPU.
>
end the TB | PATCH [03/08]
- generate_trap() for indirct jump now set | PATCH [04/08]
DISAS_NORETURN
v3 -> v4:
- Exit tb for RESTORE insn | PATCH [08/08]
Bastian Koppelmann (8):
target/tricore: Fix RR_JLI clobbering reg A[11]
target/tric
if A[r1] == A[11], then we would overwrite the destination address of
the jump with the return address.
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 025b12567a..3d0c90b3dd 100644
--- a/target/tricore/translate.c
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU. We also need to exit this tb here, as we might have enabled
interrupts.
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- Exit tb for R
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.h | 17 -
target/tricore/translate.c | 14 --
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 041fc0b6e5
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 43 +-
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1a0c6d35d3..1d570b49ff
so we can recognize exceptions after re-enabling interrupts.
Reviewed-by: Richard Henderson
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore
eviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1d570b49ff..71b6209af4 100644
--- a/target/tricore/translate.c
+++ b/targ
this replaces all calls to tcg_gen_exit_tb() and moves them to
tricore_tb_stop().
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/tricore
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.1337971-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h |
wo 32 regs
- Fix erroneously saving PSW.CDC on CALL insns
- Added some missing v1.6.2 insns
--------
Bastian Koppelmann (19):
target/tricore: Introduce ISA 1.6.2 feature
target/tricore: Add popcnt.w insn
target/tricore: Ad
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.1337971-4-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 14 --
target/tricore/tricore-opcodes.
we also introduce the tc37x CPU that implements that ISA version.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.1337971-2-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.c | 13 +
target/tricore/cpu.h | 1 +
2 files chang
we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699
Signed-off-by: Bastian Koppelmann
Message-Id: <20230612113245.56667-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 7 ++-
1 file
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <202306141
From: Siqi Chen
When translating "imask" instruction of Tricore architecture, QEMU did not
check whether the register index was out of bounds, resulting in a
global-buffer-overflow.
Reviewed-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698
R
tps://gitlab.com/qemu-project/qemu/-/issues/1700
Signed-off-by: Bastian Koppelmann
Message-Id: <20230612113245.56667-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/tricore/op_helper.c b/targe
Reviewed-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.1337971-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
so we can recognize exceptions after re-enabling interrupts.
Reviewed-by: Richard Henderson
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230621142302.1648383-4-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 5 +
1 file chan
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230621142302.1648383-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 17 -
target/tricore/translate.c | 14 --
2 files changed, 20 insertions(+), 11 deletions(-)
this replaces all calls to tcg_gen_exit_tb() and moves them to
tricore_tb_stop().
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230621142302.1648383-3-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 25 -
1 file c
if A[r1] == A[11], then we would overwrite the destination address of
the jump with the return address.
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230621142302.1648383-2-kbast...@mail.uni-paderborn.de>
---
target/t
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.1337971-6-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU. We also need to exit this tb here, as we might have enabled
interrupts.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message
some insns were not checking if an even index was used to access a 64
bit register. In the worst case that could lead to a buffer overflow as
reported in https://gitlab.com/qemu-project/qemu/-/issues/1698.
Reported-by: Siqi Chen
Signed-off-by: Bastian Koppelmann
Message-Id
this is based on code by volumit (https://github.com/volumit/qemu/).
Reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
and https://gitlab.com/qemu-project/qemu/-/issues/1452.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.133797
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230621142302.1648383-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/trans
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230614100039.1337971-5-kbast...@mail.uni-paderborn.de>
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c
eviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <20230621142302.1648383-8-kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
701 - 800 of 1418 matches
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