The following changes since commit c5ffd16ba4c8fd3601742cc9d2b3cff03995dd5d:
Revert "cputlb: Restrict SavedIOTLB to system emulation" (2023-06-21 07:19:46 +0200) are available in the Git repository at: https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230621-1 for you to fetch changes up to a9c37abdff65a07d0191123a21d318c4d8cc7f33: target/tricore: Fix ICR.IE offset in RESTORE insn (2023-06-21 18:09:54 +0200) ---------------------------------------------------------------- - Implement privilege levels for TriCore - Fix missing REG_PAIR() for insns using two 32 regs - Fix erroneously saving PSW.CDC on CALL insns - Added some missing v1.6.2 insns ---------------------------------------------------------------- Bastian Koppelmann (19): target/tricore: Introduce ISA 1.6.2 feature target/tricore: Add popcnt.w insn target/tricore: Add LHA insn target/tricore: Add crc32l.w insn target/tricore: Add crc32.b insn target/tricore: Add shuffle insn target/tricore: Implement SYCSCALL insn target/tricore: Add DISABLE insn variant target/tricore: Correctly fix saving PSW.CDE to CSA on call target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs target/tricore: Fix helper_ret() not correctly restoring PSW target/tricore: Fix RR_JLI clobbering reg A[11] target/tricore: Introduce DISAS_TARGET_EXIT target/tricore: ENABLE exit to main-loop target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr() target/tricore: Introduce priv tb flag target/tricore: Implement privilege level for all insns target/tricore: Honour privilege changes on PSW write target/tricore: Fix ICR.IE offset in RESTORE insn Siqi Chen (1): target/tricore: Fix out-of-bounds index in imask instruction target/tricore/cpu.c | 13 +++ target/tricore/cpu.h | 18 +++-- target/tricore/helper.h | 5 +- target/tricore/op_helper.c | 69 ++++++++++++++-- target/tricore/translate.c | 167 ++++++++++++++++++++++++++++++--------- target/tricore/tricore-opcodes.h | 16 +++- 6 files changed, 237 insertions(+), 51 deletions(-)
