so we can recognize exceptions after re-enabling interrupts. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reported-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> --- v2 -> v3: - DISABLE insns don't end the TB
target/tricore/translate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index d4f7415158..025b12567a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -38,6 +38,7 @@ #undef HELPER_H #define DISAS_EXIT DISAS_TARGET_0 +#define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* * TCG registers @@ -7892,6 +7893,7 @@ static void decode_sys_interrupts(DisasContext *ctx) break; case OPC2_32_SYS_ENABLE: tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; break; case OPC2_32_SYS_ISYNC: break; @@ -8379,6 +8381,9 @@ static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_TOO_MANY: gen_goto_tb(ctx, 0, ctx->base.pc_next); break; + case DISAS_EXIT_UPDATE: + gen_save_pc(ctx->base.pc_next); + /* fall through */ case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; -- 2.40.1