Hi,
Le 02/06/2016 à 14:45, Alexander Graf a écrit :
>
>
> On 02.06.16 14:32, Peter Maydell wrote:
>> On 2 June 2016 at 13:26, Bogdan Purcareata wrote:
>>> A PCI device is marked either as coherent or non-coherent based on the pcie
>>> controller "dma-coherent" property. This is further used when
Hi,
Le 22/04/2016 à 12:15, Christoffer Dall a écrit :
> On Fri, Apr 22, 2016 at 12:06:52PM +0200, Alexander Graf wrote:
>> On 04/22/2016 12:01 PM, Christoffer Dall wrote:
>>> On Thu, Apr 21, 2016 at 09:50:05PM +0200, Alexander Graf wrote:
On 21.04.16 18:23, Christoffer Dall wrote:
>
Hi Shameer,
On 5/1/19 12:40 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 30 April 2019 16:50
>> To: Shameerali Kolothum Thodi ;
>> qemu-devel@nongnu.org; qemu-...@n
Hi Shameer,
On 5/10/19 10:34 AM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-
>> From: Laszlo Ersek [mailto:ler...@redhat.com]
>> Sent: 09 May 2019 22:48
>> To: Igor Mammedov
>> Cc: Robin Murphy ; Shameerali Kolothum Thodi
>> ; will.dea...@arm.com; Catalin
>> Marinas ; Ans
Hi Shameer,
On 5/10/19 11:27 AM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 10 May 2019 10:16
>> To: Shameerali Kolothum Thodi ;
>> Laszlo Ersek ; Igor Mammedov
>&g
Hi Drew,
On 5/12/19 10:36 AM, Andrew Jones wrote:
> Allow the cpu type 'max' sve-max-vq property to work with kvm
> too. If the property is not specified then the maximum kvm
> supports is used. If it is specified we check that kvm supports
> that exact length or error out if it doesn't.
>
> Signe
Hi Alex,
On 6/11/19 9:48 PM, Alex Williamson wrote:
> On Tue, 11 Jun 2019 17:47:25 +0200
> Eric Auger wrote:
>
>> The code used to assign an interrupt index/subindex to an
>> eventfd is duplicated many times. Let's introduce an helper that
>> allows to set/unset the signaling for an ACTION_TRIGG
Hi Li,
On 6/12/19 10:24 AM, Li Qiang wrote:
> Eric Auger 于2019年6月12日周三 下午4:14写道：
>
>> The code used to assign an interrupt index/subindex to an
>> eventfd is duplicated many times. Let's introduce an helper that
>> allows to set/unset the signaling for an ACTION_TRIGGER,
>> ACTION_MASK or ACTION
Hi Connie,
On 6/12/19 6:46 PM, Cornelia Huck wrote:
> On Wed, 12 Jun 2019 14:40:04 +0200
> Eric Auger wrote:
>
>> The code used to assign an interrupt index/subindex to an
>> eventfd is duplicated many times. Let's introduce an helper that
>> allows to set/unset the signaling for an ACTION_TRIGG
Hi Li,
On 6/13/19 1:40 AM, Li Qiang wrote:
> Eric Auger 于2019年6月12日周三 下午8:40写道：
>
>> The code used to assign an interrupt index/subindex to an
>> eventfd is duplicated many times. Let's introduce an helper that
>> allows to set/unset the signaling for an ACTION_TRIGGER,
>> ACTION_MASK or ACTION_
Hi Connie,
On 6/14/19 11:27 AM, Cornelia Huck wrote:
> Use the new helper.
>
> Signed-off-by: Cornelia Huck
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/vfio/ccw.c | 68 +++
> 1 file changed, 14 insertions(+), 54 deletions(-)
>
> diff --git
Hi Peter,
On 6/14/19 3:26 PM, Peter Maydell wrote:
> On Tue, 11 Jun 2019 at 15:29, Eric Auger wrote:
>>
>> On ARM we currently do not support VFIO-PCI devices protected
>> by the IOMMU. Any attempt to run such use case results in this
>> kind of warning:
>>
>> "-device vfio-pci,host=0004:01:00.0,
Hi Peter,
On 6/14/19 3:23 PM, Peter Maydell wrote:
> On Tue, 11 Jun 2019 at 15:29, Eric Auger wrote:
>>
>> An IOVA/ASID invalidation is notified to all IOMMU Memory Regions
>> through smmuv3_inv_notifiers_iova/smmuv3_notify_iova.
>>
>> When the notification occurs it is possible that some of the
Hi Peter,
On 6/14/19 3:45 PM, Peter Maydell wrote:
> On Fri, 14 Jun 2019 at 14:40, Auger Eric wrote:
>>
>> Hi Peter,
>>
>> On 6/14/19 3:26 PM, Peter Maydell wrote:
>>> On Tue, 11 Jun 2019 at 15:29, Eric Auger wrote:
>>>>
>>>> On ARM we
Hi Eric,
On 6/14/19 4:30 PM, Eric Farman wrote:
>
>
> On 6/14/19 5:27 AM, Cornelia Huck wrote:
>> Use the new helper.
>>
>> Signed-off-by: Cornelia Huck
>> ---
>> hw/vfio/ccw.c | 68 +++
>> 1 file changed, 14 insertions(+), 54 deletions(-)
>>
>>
Hi Eduardo,
On 3/7/19 6:26 PM, Eduardo Habkost wrote:
> On Thu, Mar 07, 2019 at 10:06:39AM +0100, Eric Auger wrote:
>> As NVDIMM support is looming for ARM and SPAPR, let's
>> move the acpi_nvdimm_state to the generic machine struct
>> instead of duplicating the same code in several machines.
>> I
Hi Shameer,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> This series is an attempt to provide device memory hotplug support
> on ARM virt platform. This is based on Eric's recent works here[1]
> and carries some of the pc-dimm related patches dropped from his
> series.
>
> The kernel support for
Hi,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> From: Sebastien Boeuf
>
> By moving the definition of memory hotplug related constants used
> by ACPI for both CPU and memory, this commits allows those to be
> used from other parts of the code.
Maybe elaborate on where you intend to use them.
Hi,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> This is in preparation for adding support for ARM64 platforms
> where it doesn't use port mapped IO for ACPI IO space.
>
> Signed-off-by: Shameer Kolothum
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/acpi/memory_hotplug.c | 22 +
Hi Peter,
On 3/8/19 4:53 PM, Peter Maydell wrote:
> On Thu, 21 Feb 2019 at 14:55, Auger Eric wrote:
>>
>> Hi,
>> On 2/21/19 3:26 PM, Peter Maydell wrote:
>>> On Thu, 21 Feb 2019 at 14:20, Auger Eric wrote:
>>>> [a regression using aarch64 KVM]
>>&
Hi Philippe,
On 3/8/19 7:02 PM, Philippe Mathieu-Daudé wrote:
> hi Eric,
>
> On 3/8/19 4:25 PM, Eric Auger wrote:
>> As NVDIMM support is looming for ARM and SPAPR, let's
>> move the acpi_nvdimm_state to the generic machine struct
>> instead of duplicating the same code in several machines.
>> It
Hi Shameer,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> From: Samuel Ortiz
>
> This is to provide an acpi device interface for Arm/virt.
> This will be used by Arm/Virt to add hotplug support via
> ACPI GED device.
I think this would deserves to mention this is a skeleton or,
wouldn't it make
Hi Shameer,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> This adds support to build the aml code so that Guest can see the
s/Guest/the guest
> cold-plugged device memory.
Isn't the colplug part only related to acpi_dsdt_add_memory_hotplug()? I
understand the patch also adds some hotplug infra?
Hi Peter,
On 3/11/19 2:26 PM, Peter Maydell wrote:
> On Thu, 21 Feb 2019 at 14:20, Auger Eric wrote:
>> This commit introduces a regression when running with EDK2 FW:
>>
>> I get the following traces:
>>
>> error: kvm run failed Function not implemented
>
&g
Hi Peter,
On 3/11/19 3:55 PM, Peter Maydell wrote:
> On Mon, 11 Mar 2019 at 14:54, Auger Eric wrote:
>> yes I hit the bug with your reduced command line:
>>
>> aarch64-softmmu/qemu-system-aarch64 -M virt,gic-version=host -cpu host
>> -smp 2 -m 4G -display none --enab
Hi Shameer,
On 3/11/19 6:37 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 11 March 2019 13:32
>> To: Shameerali Kolothum Thodi ;
>> qemu-devel@nongnu.org; qemu-...@nongnu.org
Hi,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> From: Samuel Ortiz
>
> The ACPI Generic Event Device (GED) is a hardware-reduced specific
> device that handles all platform events, including the hotplug ones.
> This patch generate the AML code that defines GEDs.
s/generate/generates
> Platform
Hi Shameer,
On 3/8/19 12:42 PM, Shameer Kolothum wrote:
> This initializes the GED device with base memory and irq.
> It also configures ged memory hotplug event and builds the
> corresponding aml code.
>
> But ged irq routing to Guest is not enabled and thus hotplug
> is not yet supported.
>
>
Hi
On 3/12/19 8:49 AM, Wei Yang wrote:
> This is more proper to use PCIE_MMCFG_BUS to retrieve end_bus_number.
>
> Signed-off-by: Wei Yang
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/arm/virt-acpi-build.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm
Hi Shameer,
On 3/12/19 4:13 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-
>> From: Igor Mammedov [mailto:imamm...@redhat.com]
>> Sent: 11 March 2019 14:59
>> To: Shameerali Kolothum Thodi
>> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
>> eric.au...@redhat.com; peter
Hi Shameer,
On 3/12/19 5:39 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 12 March 2019 15:38
>> To: Shameerali Kolothum Thodi ;
>> Igor Mammedov
>> Cc: peter
Hi Shameer,
On 3/12/19 5:56 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: 12 March 2019 16:48
>> To: Shameerali Kolothum Thodi ;
>> Igor Mammedov
>> Cc: peter
Hi Juan,
On 10/17/19 10:06 AM, Juan Quintela wrote:
> Eric Auger wrote:
>> Support QLIST migration using the same principle as QTAILQ:
>> 94869d5c52 ("migration: migrate QTAILQ").
>>
>> The VMSTATE_QLIST_V macro has the same proto as VMSTATE_QTAILQ_V.
>> The change mainly resides in QLIST_RAW_INS
Hi Shameer,
On 10/4/19 5:52 PM, Shameer Kolothum wrote:
> This series adds NVDIMM support to arm/virt platform.
> This has a dependency on [0] and make use of the GED
> device for NVDIMM hotplug events. The series reuses
> some of the patches posted by Eric in his earlier
> attempt here[1].
>
> P
Hi Peter, Michael,
On 2/11/20 6:31 PM, Auger Eric wrote:
> Hi Peter,
>
> On 2/11/20 4:00 PM, Peter Maydell wrote:
>> On Sat, 8 Feb 2020 at 12:01, Eric Auger wrote:
>>>
>>> Adds the "virtio,pci-iommu" node in the host bridge node and
>>> the R
Hi Michal,
On 2/14/20 10:55 AM, Michal Privoznik wrote:
> In a few places we report errno formatted as a negative integer.
> This is not as user friendly as it can be. Use strerror() and/or
> error_setg_errno() instead.
>
> Signed-off-by: Michal Privoznik
Reviewed-by: Eric Auger
Thanks
Eric
>
Hi Philippe,
On 2/17/20 10:21 AM, Philippe Mathieu-Daudé wrote:
> Hi Eric,
>
> On 2/14/20 7:37 PM, Eric Auger wrote:
>> As we plan to introdce a SysBus TPM TIS device, let's
>> make the TPMState a common struct usable by both the
>> ISADevice and the SysBusDevice. TPMStateISA embeds the
>> struct
Hi Stefan,
On 2/16/20 7:32 PM, Stefan Berger wrote:
> On 2/14/20 1:37 PM, Eric Auger wrote:
>> Introduce the tpm-tis-device which is a sysbus device
>> and is bound to be used on ARM.
>>
>> Signed-off-by: Eric Auger
>> ---
>> hw/tpm/Kconfig | 5 ++
>> hw/tpm/Makefile.objs | 1 +
Hi Ard,
On 2/16/20 5:35 PM, Ard Biesheuvel wrote:
> On Fri, 14 Feb 2020 at 19:37, Eric Auger wrote:
>>
>> This series adds the capability to instantiate an MMIO TPM TIS
>> in ARM virt.
>>
>> The existing TPM TIS code is reshuffled into a generic part,
>> the ISA device and the sysbus device. The
Hi Stefan,
On 2/16/20 7:47 PM, Stefan Berger wrote:
> On 2/14/20 1:37 PM, Eric Auger wrote:
>> Let the TPM TIS SYSBUS device be dynamically instantiable
>> in ARM virt. A device tree node is dynamically created
>> (TPM via MMIO).
>>
>> The TPM Physical Presence interface (PPI) is not supported.
>
Hi Simon,
On 12/4/19 2:55 PM, Simon Veith wrote:
> The bit offsets in the EVT_SET_ADDR2 macro do not match those specified
> in the ARM SMMUv3 Architecture Specification. In all events that use
> this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually
> occupies the 32-bit words 6
Hi Simon,
On 12/4/19 2:55 PM, Simon Veith wrote:
> The smmuv3_record_event() function that generates the F_STE_FETCH error
> uses the EVT_SET_ADDR macro to record the fetch address, placing it in
> 32-bit words 4 and 5.
>
> The correct position for this address is in words 6 and 7, per the
> SMMU
Hi Simon,
On 12/4/19 2:55 PM, Simon Veith wrote:
> When checking whether a stream ID is in range of the stream table, we
> have so far been only checking it against our implementation limit
> (SMMU_IDR1_SIDSIZE). However, the guest can program the
> STRTAB_BASE_CFG.LOG2SIZE field to a size that is
Hi Simon,
On 12/4/19 2:55 PM, Simon Veith wrote:
> In the SMMU_STRTAB_BASE register, the stream table base address only
> occupies bits [51:6]. Other bits, such as RA (bit [62]), must be masked
> out to obtain the base address.
>
> The branch for 2-level stream tables correctly applies this mask
Hi Simon,
On 12/4/19 2:55 PM, Simon Veith wrote:
> Per the specification, and as observed in hardware, the SMMUv3 aligns
> the SMMU_STRTAB_BASE address to the size of the table by masking out the
> respective least significant bits in the ADDR field.
>
> Apply this masking logic to our smmu_find_
Hi Simon,
On 12/5/19 11:04 PM, Simon Veith wrote:
> Hello Eric,
>
> On 05/12/2019 09:42, Auger Eric wrote:
>> Not related to this patch but I noticed SMMU_BASE_ADDR_MASK should be
>> 0xffc0 and not 0xffe0. I can fix it separately or if you
>> res
Hi Michael,
On 12/11/19 5:40 PM, Michael S. Tsirkin wrote:
> On Fri, Nov 22, 2019 at 07:29:23PM +0100, Eric Auger wrote:
>> This series implements the QEMU virtio-iommu device.
>>
>> This matches the v0.12 spec and the corresponding virtio-iommu
>> driver upstreamed in 5.3.
>>
>> The pci proxy for
Hi Michael,
On 12/11/19 9:40 PM, Michael S. Tsirkin wrote:
> On Wed, Dec 11, 2019 at 05:48:05PM +0100, Auger Eric wrote:
>> Hi Michael,
>>
>> On 12/11/19 5:40 PM, Michael S. Tsirkin wrote:
>>> On Fri, Nov 22, 2019 at 07:29:23PM +0100, Eric Auger wrote:
>>>&
Hi Markus,
On 12/12/19 1:17 PM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> Introduce a new property defining a labelled interval:
>> ,,label.
>>
>> This will be used to encode reserved IOVA regions. The label
>> is left undefined to ease reuse accross use cases.
>
> What does the last s
Hi Simon,
On 12/16/19 4:15 PM, Simon Veith wrote:
> There are two issues with the current value of SMMU_BASE_ADDR_MASK:
>
> - At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec,
> we should also be treating bit 5 as zero in the base address.
> - At the upper end, we are clearing
Hi Simon,
On 12/16/19 4:15 PM, Simon Veith wrote:
> When checking whether a stream ID is in range of the stream table, we
> have so far been only checking it against our implementation limit
> (SMMU_IDR1_SIDSIZE). However, the guest can program the
> STRTAB_BASE_CFG.LOG2SIZE field to a size that i
Hi Simon,
On 12/16/19 4:15 PM, Simon Veith wrote:
> Per the specification, and as observed in hardware, the SMMUv3 aligns
> the SMMU_STRTAB_BASE address to the size of the table by masking out the
> respective least significant bits in the ADDR field.
>
> Apply this masking logic to our smmu_find
Hi,
On 12/16/19 4:15 PM, Simon Veith wrote:
> While working on the Linux SMMUv3 driver, I noticed a few cases where the QEMU
> SMMUv3 behavior relating to stream tables was inconsistent with our hardware.
>
> Also, when debugging those differences, I found that the errors reported
> through
> th
Hi Zenghui,
On 12/18/19 4:46 AM, Zenghui Yu wrote:
> Hi Eric,
>
> I have to admit that this is the first time I've looked into
> the kvm-unit-tests code, so only some minor comments inline :)
no problem. Thank you for looking at this.
By the way, with patch 16 I was able to test yout fix: "KVM:
Hi Dave,
On 11/22/19 8:03 PM, Dr. David Alan Gilbert wrote:
> * Eric Auger (eric.au...@redhat.com) wrote:
>> Introduce a new property defining a labelled interval:
>> ,,label.
>>
>> This will be used to encode reserved IOVA regions. The label
>> is left undefined to ease reuse accross use cases.
>
Hi Jean,
On 11/4/19 7:31 PM, Jean-Philippe Brucker wrote:
> Hi Eric,
>
> On Tue, Jul 30, 2019 at 07:21:28PM +0200, Eric Auger wrote:
>> static void virtio_iommu_device_unrealize(DeviceState *dev, Error **errp)
>> {
>> VirtIODevice *vdev = VIRTIO_DEVICE(dev);
>> +VirtIOIOMMU *s = VIRTIO_
Hi Kevin, Michael,
On 7/31/19 1:20 AM, Tian, Kevin wrote:
>> From: Michael S. Tsirkin [mailto:m...@redhat.com]
>> Sent: Wednesday, July 31, 2019 3:38 AM
>>
>> On Tue, Jul 30, 2019 at 07:21:33PM +0200, Eric Auger wrote:
>>> We introduce a new msi_bypass field which indicates whether
>>> the IOAPIC
Hi Michael,
On 7/31/19 9:25 PM, Michael S. Tsirkin wrote:
> On Tue, Jul 30, 2019 at 11:20:44PM +, Tian, Kevin wrote:
>>> From: Michael S. Tsirkin [mailto:m...@redhat.com]
>>> Sent: Wednesday, July 31, 2019 3:38 AM
>>>
>>> On Tue, Jul 30, 2019 at 07:21:33PM +0200, Eric Auger wrote:
We intr
Hi Michael,
On 7/30/19 9:35 PM, Michael S. Tsirkin wrote:
> On Tue, Jul 30, 2019 at 07:21:36PM +0200, Eric Auger wrote:
>> This patch adds virtio-iommu-pci, which is the pci proxy for
>> the virtio-iommu device.
>>
>> Signed-off-by: Eric Auger
>
> This part I'm not sure we should merge just yet.
Hi Michael,
On 8/1/19 3:06 PM, Michael S. Tsirkin wrote:
> On Thu, Aug 01, 2019 at 02:15:03PM +0200, Auger Eric wrote:
>> Hi Michael,
>>
>> On 7/30/19 9:35 PM, Michael S. Tsirkin wrote:
>>> On Tue, Jul 30, 2019 at 07:21:36PM +0200, Eric Auger wrote:
>>>>
Hi Yi,
On 7/26/19 7:18 AM, Liu, Yi L wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: Wednesday, July 24, 2019 5:33 PM
>> To: Liu, Yi L ; David Gibson
>>
>> Subject: Re: [RFC v1 05/18] vfi
Hi Peter,
On 2/3/20 4:19 PM, Peter Xu wrote:
> On Mon, Feb 03, 2020 at 03:59:00PM +0100, Auger Eric wrote:
>
> [...]
>
>>>> +static void virtio_iommu_detach_endpoint_from_domain(VirtIOIOMMUEndpoint
>>>> *ep)
>>>> +{
>>>> +QLIST_R
Hi Peter,
On 2/3/20 7:19 PM, Peter Xu wrote:
> On Mon, Feb 03, 2020 at 06:46:36PM +0100, Auger Eric wrote:
>> Hi Peter,
>>
>> On 2/3/20 4:19 PM, Peter Xu wrote:
>>> On Mon, Feb 03, 2020 at 03:59:00PM +0100, Auger Eric wrote:
>>
Hi Jean,
On 2/7/20 11:05 AM, Jean-Philippe Brucker wrote:
> Hi Eric,
>
> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
>> At the moment, the kernel only supports device tree
>> integration of the virtio-iommu. DT bindings between the
>> PCI root complex and the IOMMU must be created
Hi
On 2/7/20 11:24 AM, Michael S. Tsirkin wrote:
> On Fri, Feb 07, 2020 at 11:05:40AM +0100, Jean-Philippe Brucker wrote:
>> Hi Eric,
>>
>> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
>>> At the moment, the kernel only supports device tree
>>> integration of the virtio-iommu. DT bi
Hi,
On 2/7/20 11:23 AM, Michael S. Tsirkin wrote:
> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
>> At the moment, the kernel only supports device tree
>> integration of the virtio-iommu. DT bindings between the
>> PCI root complex and the IOMMU must be created by the machine
>> in
Hi Jean,
On 2/7/20 12:15 PM, Jean-Philippe Brucker wrote:
> On Fri, Feb 07, 2020 at 11:51:55AM +0100, Auger Eric wrote:
>> Hi,
>>
>> On 2/7/20 11:23 AM, Michael S. Tsirkin wrote:
>>> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
>>>> At t
Hi Michael,
On 2/7/20 1:00 PM, Michael S. Tsirkin wrote:
> On Fri, Feb 07, 2020 at 11:51:55AM +0100, Auger Eric wrote:
>> Hi,
>>
>> On 2/7/20 11:23 AM, Michael S. Tsirkin wrote:
>>> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
>>>> At t
Hi Peter,
On 2/7/20 9:26 PM, Peter Xu wrote:
> On Fri, Feb 07, 2020 at 10:31:55AM +0100, Eric Auger wrote:
>
> [...]
>
>> v13 -> v14:
>> - in virtio_iommu_put_endpoint, if the EP is attached to a
>> domain, call virtio_iommu_detach_endpoint_from_domain()
>> - remove domain ref counting and sim
Hi Peter,
On 2/8/20 2:41 PM, Peter Xu wrote:
> On Sat, Feb 08, 2020 at 01:00:16PM +0100, Eric Auger wrote:
>> This patch implements the endpoint attach/detach to/from
>> a domain.
>>
>> Domain and endpoint internal datatypes are introduced.
>> Both are stored in RB trees. The domain owns a list of
Hi Juan,
On 2/10/20 1:33 PM, Juan Quintela wrote:
> Eric Auger wrote:
>> Add Migration support. We rely on recently added gtree and qlist
>> migration. We only migrate the domain gtree. The endpoint gtree
>> is re-constructed in a post-load operation.
>>
>> Signed-off-by: Eric Auger
>
> Reviewe
Hi Juan,
On 2/10/20 2:09 PM, Auger Eric wrote:
> Hi Juan,
>
> On 2/10/20 1:33 PM, Juan Quintela wrote:
>> Eric Auger wrote:
>>> Add Migration support. We rely on recently added gtree and qlist
>>> migration. We only migrate the domain gtree. The endpoint gtre
Hi Philippe,
On 2/11/20 9:25 AM, Philippe Mathieu-Daudé wrote:
> On 2/10/20 2:15 PM, Eric Auger wrote:
>> Implement support for TPM on aarch64 by using the
>> TPM TIS MMIO frontend. Instead of being an ISA device,
>> the TPM TIS device becomes a sysbus device on ARM. It is
>> bound to be dynamical
Hi Peter,
On 2/11/20 11:56 AM, Peter Maydell wrote:
> On Tue, 11 Feb 2020 at 08:35, Auger Eric wrote:
>>
>> Hi Philippe,
>>
>> On 2/11/20 9:25 AM, Philippe Mathieu-Daudé wrote:
>>> You don't need much to remove the RFC tag:
>>>
>>> - re
Hi Peter,
On 2/11/20 4:00 PM, Peter Maydell wrote:
> On Sat, 8 Feb 2020 at 12:01, Eric Auger wrote:
>>
>> Adds the "virtio,pci-iommu" node in the host bridge node and
>> the RID mapping, excluding the IOMMU RID.
>>
>> This is done in the virtio-iommu-pci hotplug handler which
>> gets called only
Hi Peter,
On 2/11/20 4:33 PM, Peter Maydell wrote:
> On Thu, 30 Jan 2020 at 11:25, Eric Auger wrote:
>>
>> If event counters are implemented check the common events
>> required by the PMUv3 are implemented.
>>
>> Some are unconditionally required (SW_INCR, CPU_CYCLES,
>> either INST_RETIRED or IN
On 2/11/20 5:07 PM, Andrew Jones wrote:
> On Tue, Feb 11, 2020 at 03:42:38PM +, Peter Maydell wrote:
>> On Thu, 30 Jan 2020 at 11:25, Eric Auger wrote:
>>>
>>> This series implements tests exercising the PMUv3 event counters.
>>> It tests both the 32-bit and 64-bit versions. Overflow interr
Hi Peter,
On 2/11/20 5:24 PM, Peter Maydell wrote:
> On Thu, 30 Jan 2020 at 11:26, Eric Auger wrote:
>>
>> Add 2 tests exercising chained counters. The first one uses
>> CPU_CYCLES and the second one uses SW_INCR.
>>
>> Signed-off-by: Eric Auger
>> +static void test_chained_sw_incr(void)
>> +{
>
Hi Peter,
On 2/11/20 5:28 PM, Peter Maydell wrote:
> On Thu, 30 Jan 2020 at 11:25, Eric Auger wrote:
>>
>> If event counters are implemented check the common events
>> required by the PMUv3 are implemented.
>>
>> Some are unconditionally required (SW_INCR, CPU_CYCLES,
>> either INST_RETIRED or IN
Hi Peter,
On 2/11/20 5:27 PM, Peter Maydell wrote:
> On Thu, 30 Jan 2020 at 11:26, Eric Auger wrote:
>>
>> Adds the following tests:
>> - event-counter-config: test event counter configuration
>> - basic-event-count:
>> - programs counters #0 and #1 to count 2 required events
>> (resp. CPU_CY
too, we have to explicitly pass around
> the iov length now.
>
> Reported-by: Auger Eric
> Signed-off-by: Gerd Hoffmann
> ---
> include/hw/virtio/virtio-gpu.h | 3 +-
> hw/display/virtio-gpu-3d.c | 7 ++--
> hw/display/virtio-gpu.c| 75 +++
Hi Peter,
On 5/10/21 1:31 PM, Peter Maydell wrote:
> On Wed, 21 Apr 2021 at 18:29, Eric Auger wrote:
>>
>> 6d9cd115b9 ("hw/arm/smmuv3: Enforce invalidation on a power of two range")
>> failed to completely fix misalignment issues with range
>> invalidation. For instance invalidations patterns lik
Hi Stefan,
On 01/11/2016 16:28, Stefan Weil wrote:
> translater -> translator (found by codespell)
Actually GITS_TRANSLATER is the terminology used for this register in
the ARM GIC architecture specification (IHI0069B).
Thanks
Eric
>
> Signed-off-by: Stefan Weil
> ---
> hw/intc/arm_gicv3_its
t; (r));\
> + return (type)r; \
> }
> -DEFINE_GET_SYSREG32(mpidr)
> +#define DEFINE_GET_SYSREG32(reg) DEFINE_GET_SYSREG(reg, unsigned int)
> +#define DEFINE_GET_SYSREG64(reg) DEFINE_GET_SYSREG(reg, unsigned long)
> +
> +DEFINE_GET_SYSREG64(mpidr)
>
> /* Only support Aff0 for now, gicv2 only */
> #define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff))
>
Reviewed-by: Eric Auger
Eric
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Make implementation equivalent to Linux's include/linux/stringify.h
>
> Signed-off-by: Andrew Jones
> ---
> lib/libcflat.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/libcflat.h b/lib/libcflat.h
> index 72
Hi Drew,
Proper commit message?
... also selects the vgic model corresponding to the host
> Reviewed-by: Alex Bennée
> Signed-off-by: Andrew Jones
> ---
> arm/run | 19 ---
> arm/selftest.c| 5 -
> lib/arm/asm/processor.h | 9 +++--
> li
Hi Prem,
On 22/08/2016 18:17, Prem Mallappa wrote:
> v1 -> v2:
> - Adopted review comments from Eric Auger
Although I am really interested in your series, those comments are not
mine and credit should be given to somebody else (Edgar?)
I will do my utmost to review it too ;-)
Thanks
Eric
>
Hi Drew,
On 30/08/2016 16:28, Auger Eric wrote:
> Hi Drew,
>
> Proper commit message?
> ... also selects the vgic model corresponding to the host
>> Reviewed-by: Alex Bennée
>> Signed-off-by: Andrew Jones
>> ---
>> arm/run | 19 ++
>
> static const char *vector_names[] = {
> "el1t_sync",
> @@ -253,3 +254,17 @@ bool is_user(void)
> {
> return current_thread_info()->flags & TIF_USER_MODE;
> }
> +
> +void delay(u64 cycles)
> +{
> + u64 start = get_cntvct();
> + while ((get_cntvct() - start) < cycles)
> + cpu_relax();
> +}
> +
> +void udelay(unsigned long usec)
> +{
> + unsigned int frq;
> + asm volatile("mrs %0, cntfrq_el0" : "=r" (frq));
> + delay((u64)usec * frq / 100);
> +}
>
Reviewed-by: Eric Auger
Eric
tatic inline void local_irq_disable(void)
> +{
> + asm volatile("msr daifset, #2" : : : "memory");
> +}
> +
> #define DEFINE_GET_SYSREG(reg, type) \
> static inline type get_##reg(void) \
> {\
>
Besides the non existing commit msg - looks like the kvm-unit-tests
practices are different from kernel ones ;-)-,
Reviewed-by: Eric Auger
Eric
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v2: configure irqs as NS GRP1
> ---
> lib/arm/asm/arch_gicv3.h | 184 ++
> lib/arm/asm/gic-v3.h | 321
> +
> lib/arm/asm/gic.h
On 15/07/2016 15:00, Andrew Jones wrote:
> Add some gicv2 support. This just adds init and enable
> functions, allowing unit tests to start messing with it.
>
> Signed-off-by: Andrew Jones
> ---
> arm/Makefile.common| 1 +
> lib/arm/asm/gic-v2.h | 74
> +
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v2: use IRM for gicv3 broadcast
> ---
> arm/gic.c | 157
> ++
> arm/unittests.cfg | 6 +++
> 2 files changed, 154 insertions(+), 9 deletions(-
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
> ---
> v2: add more details in the output if a test fails,
> report spurious interrupts if we get them
> ---
> arm/Makefile.common | 6 +-
> arm/gic.c | 194
> +++
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Allow user to select who sends ipis and with which irq,
> rather than just always sending irq=0 from cpu0.
>
> Signed-off-by: Andrew Jones
>
> ---
> v2: actually check that the irq received was the irq sent,
> and (for gicv2) that the send
Hi Wei,
On 02/09/2016 23:46, Wei Huang wrote:
> Current QEMU will stall guest VM booting under ACPI mode when vcpu count
> is >= 12. Analyzing the booting log, it turns out that DSDT table can't
> be loaded correctly due to "Invalid character(s) in name (0x62303043),
> repaired: [C00*]". This is b
Hi Prem,
On 22/08/2016 18:17, Prem Mallappa wrote:
> Added ACPI IORT tables, was needed for internal project purpose, but
> posting here for anyone looking for testing ACPI on ARM platforms.
> (P.S: Linux side IORT patches are WIP)
I am also interested in IORT ITS group and currently prototyping
s
Hi Prem,
Missing commit message
> Signed-off-by: Prem Mallappa
> ---
> include/qemu/log.h | 1 +
> util/log.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/include/qemu/log.h b/include/qemu/log.h
> index 234fa81..3dd2131 100644
> --- a/include/qemu/log.h
> +++ b/include/q
Hi Prem,
> SMMUv3 needs device tree entry like below
To me the commit message should be more explicit and mention appendprop
functionality
>
> interrupt-names = "gerror", "priq", "eventq", "cmdq-sync";
>
> This patch introduces helper function to add entries like above
>
> Signed-off-by: P
Hi Prem,
> Default virt platform now creates SMMU device.
> Default config to build SMMU device along is in previous patches.
>
> Signed-off-by: Prem Mallappa
> ---
> hw/arm/virt.c | 62
> +++
> include/hw/arm/smmu.h | 33
1 - 100 of 1369 matches
Mail list logo
