On 9 September 2014 11:14, Peter Maydell wrote:
> On 5 September 2014 16:15, Ard Biesheuvel wrote:
>> When booting with -bios or -pflash rather than -kernel, we need to make sure
>> reset handlers are registered.
>>
>> Signed-off-by: Ard Biesheuvel
>> ---
>
On 17 September 2014 10:14, Andreas Färber wrote:
> Am 17.09.2014 um 18:47 schrieb Peter Maydell:
>> On 17 September 2014 09:40, Andreas Färber wrote:
>>> We avoided that by not using DeviceClass::reset but CPUClass::reset.
>>> It's a question of assuring appropriate reset ordering between CPU an
On 18 September 2014 05:18, Laszlo Ersek wrote:
> On 09/18/14 13:44, Andreas Färber wrote:
>> Hello Laszlo,
>>
>> Am 18.09.2014 um 10:23 schrieb Laszlo Ersek:
>>> I've been made an offer that I couldn't refuse :) to "organize" a Birds
>>> of a Feather session concerning OVMF at the KVM Forum 2014.
On 19 September 2014 10:03, Paolo Bonzini wrote:
> Il 19/09/2014 16:17, Ard Biesheuvel ha scritto:
>>
>>> > (**) Ard's patches for the upstream host kernel (== KVM) have been...
>>> > ugh, not sure... applied to a maintainer tree? Ard? :)
>>> >
If we are running the 'virt' machine, we may have a device tree blob but no
kernel to supply it to if no -kernel option was passed. In that case, copy it
to the base of DRAM where it can be picked up by a bootloader executing from
NOR flash.
Signed-off-by: Ard Biesheuvel
---
hw/arm/
ing this up while I was away. I have tested your
version of the series, and my test cases still appear to work
correctly.
However, we still haven't addressed the CPU reset case, so issuing the
PSCI reset under -bios does nothing.
Latest is here
http://marc.info/?l=qemu-devel&m=140993015
On 10 October 2014 12:56, Peter Maydell wrote:
> On 10 October 2014 11:42, Ard Biesheuvel wrote:
>> Thanks for picking this up while I was away. I have tested your
>> version of the series, and my test cases still appear to work
>> correctly.
>
> Do you see the odd
Move the registering of CPU reset handlers to before the point where
we leave the function in the -bios (not -kernel) case, so CPU reset
works correctly with -bios as well.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff
On 10 October 2014 13:22, Peter Maydell wrote:
> On 10 October 2014 12:02, Ard Biesheuvel wrote:
>> On 10 October 2014 12:56, Peter Maydell wrote:
>>> Do you see the odd behaviour after guest reset for 32
>>> bit SMP cores?
>>>
>>
>> I will tr
Move the registering of CPU reset handlers to before the point where
we leave the function in the -bios (not -kernel) case, so CPU reset
works correctly with -bios as well.
Signed-off-by: Ard Biesheuvel
---
Changes since v2:
- split into two loops again, as the boot_info field must not be
> Dear all,
>
> The goal of this mail is to summarize how dynamic sysbus device tree
> nodes were created on ARM with "machvirt dynamic sysbus device
> instantiation",
> https://lists.gnu.org/archive/html/qemu-devel/2014-09/msg01626.html
> and request some advises after commit "hw/arm/boot: load DT
Add a property "linux,stdout-path" to the /chosen DT node and make
it point to the emulated UART. This allows users such as the Linux
kernel to produce console output without the need to pass console=
or earlycon=pl011,0x... command line arguments.
Signed-off-by: Ard Biesheuvel
-
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c
ff-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/Makefile.objs | 1 +
target-arm/cpu-qom.h | 6 ++
target-arm/cpu.c | 10 +++-
target-arm/cpu.h | 6 ++
target-arm/helper.c | 12
target-arm/psci.c
From: Rob Herring
Add AArch64 support to arm_cpu_set_pc and make it available to other files.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu.c | 7 ---
target-arm/cpu.h | 12
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/target
This series adds PSCI support to ARM and AArch64 system emulation when running
in TCG mode. As PSCI calls can be made using either hypervisor call (HVC) or
secure monitor call (SMC) instructions, support is added for handling those
in patch #3 before patch #4 adds the actual PSCI dispatch logic. Pa
From: Rob Herring
Add the infrastructure to handle and emulate hvc and smc exceptions.
This will enable emulation of things such as PSCI calls. This commit
does not change the behavior and will exit with unknown exception.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI no longer
needs to be a KVM only feature.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
hw/arm/virt.c | 70
On 1 September 2014 11:09, Peter Maydell wrote:
> On 1 September 2014 08:53, Ard Biesheuvel wrote:
>> From: Rob Herring
>>
>> Add AArch64 support to arm_cpu_set_pc and make it available to other files.
>
> This is still the wrong way to do this. See review on
> pre
ff-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu64.c | 2 ++
target-arm/helper-a64.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index aa42803959be..9f88b9f4eea0 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
This series adds PSCI support to ARM and AArch64 system emulation when running
in TCG mode. As PSCI calls can be made using either hypervisor call (HVC) or
secure monitor call (SMC) instructions, support is added for handling those
in patch #3 before patch #4 adds the actual PSCI dispatch logic. Pa
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c
From: Rob Herring
Add the infrastructure to handle and emulate hvc and smc exceptions.
This will enable emulation of things such as PSCI calls. This commit
does not change the behavior and will exit with unknown exception.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target
ff-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/Makefile.objs | 1 +
target-arm/cpu-qom.h | 6 ++
target-arm/cpu.c | 10 ++-
target-arm/cpu.h | 6 ++
target-arm/helper.c | 12
target-arm/psci.c| 172
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI no longer
needs to be a KVM only feature.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
hw/arm/virt.c | 70
On 1 September 2014 15:50, Peter Maydell wrote:
> On 1 September 2014 12:55, Ard Biesheuvel wrote:
>> Currently, booting multiple cores under TCG is unstable, so the restriction
>> to 1 cpu in TCG mode is retained for now. However, PSCI reset and poweroff
>> are
>
On 1 September 2014 14:04, Peter Maydell wrote:
> On 1 September 2014 12:55, Ard Biesheuvel wrote:
>> From: Rob Herring
>>
>> Add support for handling PSCI calls in system emulation. Both version
>> 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable
On 1 September 2014 19:36, Peter Maydell wrote:
> On 26 August 2014 16:31, Ard Biesheuvel wrote:
>> If we are running the 'virt' machine, we may have a device tree blob but no
>> kernel to supply it to if no -kernel option was passed. In that case, copy it
>> to t
On 1 September 2014 13:55, Ard Biesheuvel wrote:
> From: Rob Herring
>
> Add the infrastructure to handle and emulate hvc and smc exceptions.
> This will enable emulation of things such as PSCI calls. This commit
> does not change the behavior and will exit with unknown exception.
On 1 September 2014 19:50, Peter Maydell wrote:
> On 1 September 2014 18:46, Ard Biesheuvel wrote:
>> On 1 September 2014 19:36, Peter Maydell wrote:
>>> On 26 August 2014 16:31, Ard Biesheuvel wrote:
>>>> If we are running the 'virt' machine, we may ha
If we are running the 'virt' machine, we may have a device tree blob but no
kernel to supply it to if no -kernel option was passed. In that case, copy it
to the base of DRAM where it can be picked up by a bootloader executing from
NOR flash.
Signed-off-by: Ard Biesheuvel
---
v2: com
This adds some PSCI function IDs and symbolic return codes that are needed
to implement PSCI emulation in TCG mode.
Signed-off-by: Ard Biesheuvel
---
target-arm/kvm-consts.h | 40
1 file changed, 40 insertions(+)
diff --git a/target-arm/kvm-consts.h b
constants we
refer to in the PSCI emulation, this is needed so QEMU can be built in
environments that don't supply the PSCI header file.
Changes since v1:
- processed first round of review, that was already given when this series was
sent out by Rob himself back in May
Ard Biesheuv
ff-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu64.c | 2 ++
target-arm/helper-a64.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index aa42803959be..9f88b9f4eea0 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI no longer
needs to be a KVM only feature.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
hw/arm/virt.c | 70
ff-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/Makefile.objs | 1 +
target-arm/cpu-qom.h | 6 ++
target-arm/cpu.c | 10 ++-
target-arm/cpu.h | 6 ++
target-arm/helper.c | 12
target-arm/psci.c| 171
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c
From: Rob Herring
Add the infrastructure to handle and emulate hvc and smc exceptions.
This will enable emulation of things such as PSCI calls. This commit
does not change the behavior and will exit with unknown exception.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target
Add support for loading DTB images when booting ELF images via -kernel.
The DTB image is located at the next 4 KB boundary above the highest address
covered by the loaded ELF image.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 18 --
1 file changed, 16 insertions(+), 2
If we are running the 'virt' machine, we may have a device tree blob but no
kernel to supply it to if no -kernel option was passed. In that case, copy it
to the base of RAM where it can be picked up by a bootloader.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 10 ++
1 fi
When booting with -bios or -pflash rather than -kernel, we need to make sure
reset handlers are registered.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 8f5649a250fd..0cfc11d42962 100644
--- a/hw/arm
Add a dtb_size output parameter to load_dtb() so that we can find out
what its memory footprint is.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e32f2f415885..c103a8fdc941 100644
From: Peter Maydell
Add two flash devices to the virt board, so that it can be used for
running guests which want a bootrom image such as UEFI. We provide
two flash devices to make it more convenient to provide both a
read-only UEFI image and a read-write place to store guest-set
UEFI config vari
quest()
has no apparent effect at all.
Patch #5 modifies load_dtb() so that it uses rom_add_blob_fixed() to load the
DTB, in order to make sure the DTB is available again at the expected offset
after a system reset.
Ard Biesheuvel (5):
hw/arm/boot: return size of loaded DTB from load_dtb()
h
In order to make the device tree blob (DTB) available in memory not only at
first boot, but also after system reset, use rom_blob_add_fixed() to install
it into memory.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm
> On 5 sep. 2014, at 17:15, Ard Biesheuvel wrote:
>
> Add support for loading DTB images when booting ELF images via -kernel.
> The DTB image is located at the next 4 KB boundary above the highest address
> covered by the loaded ELF image.
>
Apologies, this commit message i
On 9 September 2014 17:25, Peter Maydell wrote:
> On 5 September 2014 13:24, Ard Biesheuvel wrote:
>> From: Rob Herring
>>
>> User mode emulation should never get interrupts and thus should not
>> use the system emulation exception handler function. Remove the
On 9 September 2014 17:28, Peter Maydell wrote:
> On 5 September 2014 13:24, Ard Biesheuvel wrote:
>> This adds some PSCI function IDs and symbolic return codes that are needed
>> to implement PSCI emulation in TCG mode.
>>
>> Signed-off-by: Ard Biesheuvel
>>
On 9 September 2014 19:17, Peter Maydell wrote:
> On 5 September 2014 13:24, Ard Biesheuvel wrote:
>> From: Rob Herring
>>
>> Add support for handling PSCI calls in system emulation. Both version
>> 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable
On 9 September 2014 20:08, Peter Maydell wrote:
> On 5 September 2014 16:15, Ard Biesheuvel wrote:
>> Add support for loading DTB images when booting ELF images via -kernel.
>> The DTB image is located at the next 4 KB boundary above the highest address
>> covered by
On 9 September 2014 20:17, Peter Maydell wrote:
> On 9 September 2014 19:15, Ard Biesheuvel wrote:
>> On 9 September 2014 20:08, Peter Maydell wrote:
>>> (Thinking about it, that implies we either need a
>>> rom_del_blob() or we need to tell load_dtb() about
>>
On 9 September 2014 19:45, Peter Maydell wrote:
> On 5 September 2014 13:24, Ard Biesheuvel wrote:
>> From: Rob Herring
>>
>> Add the infrastructure to handle and emulate hvc and smc exceptions.
>> This will enable emulation of things such as PSCI calls. This co
On 9 September 2014 23:59, Peter Maydell wrote:
> On 9 September 2014 22:51, Ard Biesheuvel wrote:
>> On 9 September 2014 19:45, Peter Maydell wrote:
>>> This is my suggestion for the best compromise between
>>> "theoretical perfect fidelity to the architect
ff-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu.c| 2 +-
target-arm/cpu64.c | 2 ++
target-arm/helper-a64.c | 3 +++
target-arm/helper.c | 5 -
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index b4
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu
From: Rob Herring
Add the infrastructure to handle and emulate hvc and smc exceptions.
This will enable emulation of things such as PSCI calls. This commit
does not change the behavior and will exit with unknown exception.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target
ned-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
target-arm/Makefile.objs | 1 +
target-arm/cpu-qom.h | 6 ++
target-arm/cpu.c | 10 ++-
target-arm/cpu.h | 6 ++
target-arm/helper.c| 12 +++
target-arm/psci.c
at don't supply the PSCI header file.
Changes since v1:
- processed first round of review, that was already given when this series was
sent out by Rob himself back in May
*** BLURB HERE ***
Ard Biesheuvel (1):
target-arm: add missing PSCI constants needed for PSCI emulation
Rob Herri
This adds some PSCI function IDs and symbolic return codes that are needed
to implement PSCI emulation in TCG mode.
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
---
target-arm/kvm-consts.h | 40
1 file changed, 40 insertions(+)
diff --git a
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI no longer
needs to be a KVM only feature.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
---
hw/arm/virt.c | 82
On 9 September 2014 20:20, Peter Maydell wrote:
> On 5 September 2014 16:15, Ard Biesheuvel wrote:
>> From: Peter Maydell
>>
>> Add two flash devices to the virt board, so that it can be used for
>> running guests which want a bootrom image such as UEFI. We provide
&
On 10 September 2014 11:12, Peter Maydell wrote:
> On 10 September 2014 10:09, Ard Biesheuvel wrote:
>> On 9 September 2014 20:20, Peter Maydell wrote:
>>> There were previously questions about whether we should
>>> have flash or RAM at the bottom, but I think it mak
On 10 September 2014 12:43, Christoffer Dall
wrote:
> On Tue, Sep 09, 2014 at 03:53:43PM +0100, Peter Maydell wrote:
>> The pl011 and pl031 devices both use level triggered interrupts,
>> but the device tree we construct was incorrectly telling the
>> kernel to configure the GIC to treat them as e
In order to make the device tree blob (DTB) available in memory not only at
first boot, but also after system reset, use rom_blob_add_fixed() to install
it into memory.
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 5 -
1 file changed, 4 insertions(+), 1
Add an address limit input parameter to load_dtb() so that we can
tell it how much memory the dtb is allowed to consume. If the dtb
doesn't fit, return 0, otherwise return the actual size of the
loaded dtb, or -1 on error.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 16 +-
ceed without it
- reshuffled order, added R-b to #1
Ard Biesheuvel (4):
hw/arm/boot: load DTB as a ROM image
hw/arm/boot: pass an address limit to and return size from load_dtb()
hw/arm/boot: load device tree to base of DRAM if no -kernel option was
passed
hw/arm/boot: enable DTB support w
Add support for loading DTB images when booting ELF images using
-kernel. If there are no conflicts with the placement of the ELF
segments, the DTB image is loaded at the base of RAM.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 16 ++--
1 file changed, 14 insertions(+), 2
If we are running the 'virt' machine, we may have a device tree blob but no
kernel to supply it to if no -kernel option was passed. In that case, copy it
to the base of RAM where it can be picked up by a bootloader.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 10 ++
1 fi
On 10 September 2014 13:21, Peter Maydell wrote:
> On 10 September 2014 11:59, Ard Biesheuvel wrote:
>> Add support for loading DTB images when booting ELF images using
>> -kernel. If there are no conflicts with the placement of the ELF
>> segments, the DTB image is load
ed some
patches from Rob that I needed for reset and poweroff under UEFI, and
I had no idea there was so much in flight already.
--
Ard.
>
> On 9 September 2014 16:59, Peter Maydell wrote:
>>
>> On 9 September 2014 22:51, Ard Biesheuvel
>> wrote:
>> >
e ELF case only because the DTB clashes with the ELF segments,
in that case, just proceed without it
- reshuffled order, added R-b to #1
Ard Biesheuvel (4):
hw/arm/boot: load DTB as a ROM image
hw/arm/boot: pass an address limit to and return size from load_dtb()
hw/arm/boot: load device tree
If we are running the 'virt' machine, we may have a device tree blob but no
kernel to supply it to if no -kernel option was passed. In that case, copy it
to the base of RAM where it can be picked up by a bootloader.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 10 ++
1 fi
Add an address limit input parameter to load_dtb() so that we can
tell load_dtb() how much memory the dtb is allowed to consume. If
the dtb doesn't fit, return 0, otherwise return the actual size of
the loaded dtb.
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c
Add support for loading DTB images when booting ELF images using
-kernel. If there are no conflicts with the placement of the ELF
segments, the DTB image is loaded at the base of RAM.
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 22 --
1 file changed, 20 insertions
In order to make the device tree blob (DTB) available in memory not only at
first boot, but also after system reset, use rom_blob_add_fixed() to install
it into memory.
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
---
hw/arm/boot.c | 5 -
1 file changed, 4 insertions(+), 1
On 25 July 2014 10:54, Riku Voipio wrote:
> On Tue, Jul 22, 2014 at 10:22:15PM -, Peter Maydell wrote:
>> On 22 July 2014 20:46, Richard Henderson wrote:
>> > On 07/21/2014 10:37 AM, Peter Maydell wrote:
>> >>> It's trying to measure clock cycles required to perform the startup
>> >>> relocat
This adds support for the SHA1 and SHA256 instructions that are available
on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel
---
target-arm/cpu.c | 2 +
target-arm/cpu.h | 2 +
target-arm/crypto_helper.c | 257
This adds support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication
instruction, which is an optional feature that is part of the v8 Crypto
Extensions.
Signed-off-by: Ard Biesheuvel
---
This is an incremental patch on top of the SHA-1/SHA-256 patch I sent earlier
this week.
target
On 27 March 2014 11:55, Peter Maydell wrote:
> On 27 March 2014 09:29, Ard Biesheuvel wrote:
>> This adds support for the VMULL.P64 polynomial 64x64 to 128 bit
>> multiplication
>> instruction, which is an optional feature that is part of the v8 Crypto
>> Ex
On 2 December 2013 17:06, Peter Maydell wrote:
> On 6 November 2013 14:21, Ard Biesheuvel wrote:
>> This adds support for the AESE/AESD/AESMC/AESIMC instructions that
>> are available on some v8 implementations of Aarch32.
>>
>> Signed-off-by: Ard Biesheuvel
>
This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel
---
Changes since v1:
- refactored AES code:
* use precomputed lookup tables for AESMC and AESIMC
* squash leaf functions add_sub_shift() and
On 10 December 2013 13:18, Aurelien Jarno wrote:
> On Thu, Dec 05, 2013 at 06:54:38PM +0100, Ard Biesheuvel wrote:
>> This adds support for the AESE/AESD/AESMC/AESIMC instructions that
>> are available on some v8 implementations of Aarch32.
>>
[...]
> All the tables to
This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel
---
target-arm/Makefile.objs | 1 +
target-arm/cpu.c | 1 +
target-arm/cpu.h | 1 +
target-arm/crypto_helper.c | 172
Ping?
Regards,
Ard.
On 6 November 2013 15:21, Ard Biesheuvel wrote:
> This adds support for the AESE/AESD/AESMC/AESIMC instructions that
> are available on some v8 implementations of Aarch32.
>
> Signed-off-by: Ard Biesheuvel
> ---
> target-arm/Makefile.objs | 1 +
&
On 31 December 2014 at 17:37, Peter Maydell wrote:
> On 31 December 2014 at 17:17, Peter Maydell wrote:
>> One thing I did notice in the dmesg:
>>
>> [ 35.798423] alg: hash: Test 1 failed for sha1-ce
>> [ 35.799135] : d3 5b 9a 85 7f 18 48 21 97 5c 12 72 a8 96 62 88
>> [ 35.799815] 0
> On 31 dec. 2014, at 18:25, Peter Maydell wrote:
>
>> On 31 December 2014 at 18:08, Ard Biesheuvel
>> wrote:
>>> On 31 December 2014 at 17:37, Peter Maydell
>>> wrote:
>>> It doesn't happen on LE TCG hosts. Joy :-)
>
>> I will
between LE and BE when reading and writing the
registers, as the SHA code performs word additions, so instead, add
array accessors for the CRYPTO_STATE type whose LE and BE specific
implementations ensure that the correct array elements are referenced.
Signed-off-by: Ard Biesheuvel
---
Only tested on
On 2 January 2015 at 15:17, Laszlo Ersek wrote:
> On 01/02/15 15:18, Ard Biesheuvel wrote:
>> The crypto emulation code in target-arm/crypto_helper.c never worked
>> correctly on big endian hosts, due to the fact that it uses a union
>> of array types to convert between th
On 5 January 2015 at 12:34, Peter Maydell wrote:
> On 2 January 2015 at 19:21, Ard Biesheuvel wrote:
>> I think the union type may have been a mistake to
>> begin with, because it introduces endianness dependencies that don't
>> actually exist in the code. It probably
This updates the Linux header to version 3.18-rc5, adding support for
(among other things) read-only memslots on ARM and arm64.
Signed-off-by: Ard Biesheuvel
---
linux-headers/asm-arm/kvm.h | 2 ++
linux-headers/asm-arm64/kvm.h | 2 ++
linux-headers/asm-powerpc/kvm.h | 6 ++
linux
On 17 November 2014 19:32, Peter Maydell wrote:
> On 17 November 2014 18:28, Ard Biesheuvel wrote:
>> This updates the Linux header to version 3.18-rc5, adding support for
>> (among other things) read-only memslots on ARM and arm64.
>>
>> Signed-off-by: Ard Biesheuve
x,stdout-path property redundant. Change the DT setup for ARM virt
> to use the generic property - supported by Linux since 3.15.
>
> Signed-off-by: Leif Lindholm
Acked-by: Ard Biesheuvel
Note that for the original patch
$ git log --oneline f022b8e95379b
f022b8e95379 hw/arm/virt: a
On 14 May 2015 at 16:41, Michael S. Tsirkin wrote:
> On Thu, May 14, 2015 at 04:19:23PM +0200, Laszlo Ersek wrote:
>> On 05/14/15 15:48, Michael S. Tsirkin wrote:
>> > On Thu, May 14, 2015 at 03:32:10PM +0200, Laszlo Ersek wrote:
>> >> On 05/14/15 15:00, Andrew Jones wrote:
>> >>> On Thu, May 14,
ing before parsing it, and free it directly
afterwards.
Signed-off-by: Ard Biesheuvel
---
hw/arm/virt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 69f51ac0da58..f8a6c46323dc 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -75
On 3 March 2015 at 19:25, Greg Bellows wrote:
>
>
> On Tue, Mar 3, 2015 at 11:06 AM, Ard Biesheuvel
> wrote:
>>
>> The recently introduced feature that allows 32 bit guests to be
>> executed under KVM on a 64-bit host incorrectly handles the case
>> where more
On 4 March 2015 at 08:10, Ard Biesheuvel wrote:
> On 3 March 2015 at 19:25, Greg Bellows wrote:
>>
>>
>> On Tue, Mar 3, 2015 at 11:06 AM, Ard Biesheuvel
>> wrote:
>>>
>>> The recently introduced feature that allows 32 bit guests to be
>>> e
On 29 May 2014 18:46, Peter Maydell wrote:
> On 25 March 2014 16:27, Ard Biesheuvel wrote:
>> This adds support for the SHA1 and SHA256 instructions that are available
>> on some v8 implementations of Aarch32.
>>
>> Signed-off-by: Ard Biesheuvel
>
> Apologies
On 29 September 2015 at 20:26, Gabriel L. Somlo wrote:
> On Tue, Sep 29, 2015 at 12:40:16PM +0200, Laszlo Ersek wrote:
>> On 09/27/15 23:29, Gabriel L. Somlo wrote:
>> > Add a fw_cfg device node to the ACPI DSDT. This is mostly
>> > informational, as the authoritative fw_cfg MMIO region(s)
>> > ar
On 1 October 2015 at 14:22, Gabriel L. Somlo wrote:
> On Wed, Sep 30, 2015 at 12:21:08PM +0200, Laszlo Ersek wrote:
>> On 09/30/15 11:59, Ard Biesheuvel wrote:
>> > On 29 September 2015 at 20:26, Gabriel L. Somlo wrote:
>> >> On Tue, Sep 29, 2015 at 12:40:
On 13 January 2016 at 11:18, Laszlo Ersek wrote:
> On 01/12/16 16:24, Shannon Zhao wrote:
>> When booting VM through UEFI, UEFI takes ownership of the RTC hardware.
>> To DTB UEFI could call libfdt api to disable the RTC device node, but to
>> ACPI it couldn't do that. Therefore, we don't generate
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