On 10 December 2013 13:18, Aurelien Jarno <aurel...@aurel32.net> wrote: > On Thu, Dec 05, 2013 at 06:54:38PM +0100, Ard Biesheuvel wrote: >> This adds support for the AESE/AESD/AESMC/AESIMC instructions that >> are available on some v8 implementations of Aarch32. >>
[...] > All the tables to support AES instructions are available in util/aes.c > and accessible by including <qemu/aes.h>. You should use that instead > of including another set of tables. > > Commit d640045a3ede028293b83e57e9ae1ce4f81044b8 gives you an example on > how it has been done for AES-NI instructions. > Unfortunately, this is not entirely the case. The sbox could potentially be reused from util/aes.c, but the mixcolumns tables are different [AES-NI wraps the entire round into a single instruction, whereas ARM uses combinations of aese/aesmc (or aesd/aesimc) for the inner rounds and aese/eor (or aesd/eor) for the final round] So if you prefer, I could replace the sbox[] with references to AES_Te4 and AES_Td4, but as it is only a partial solution, I would prefer to keep it as is. (Also, the implementation is a bit strange: the sbox elements are duplicated 4 times in each word of AES_Te4/AES_Td4, so we are clobbering 4 times as many cachelines as necessary) Regards, Ard.
