This series adds PSCI support to ARM and AArch64 system emulation when running
in TCG mode. As PSCI calls can be made using either hypervisor call (HVC) or
secure monitor call (SMC) instructions, support is added for handling those
in patch #3 before patch #5 adds the actual PSCI dispatch logic. Patch #6
enables PSCI for the mach-virt platform.
Currently, booting multiple cores under TCG is unstable, so the restriction
to 1 cpu in TCG mode is retained for now. However, PSCI reset and poweroff are
supported.
Changes since v2:
- added path #4 to introduce QEMU counterparts of the kernel PSCI constants we
refer to in the PSCI emulation, this is needed so QEMU can be built in
environments that don't supply the PSCI header file.
Changes since v1:
- processed first round of review, that was already given when this series was
sent out by Rob himself back in May
Ard Biesheuvel (1):
target-arm: add missing PSCI constants needed for PSCI emulation
Rob Herring (5):
target-arm: add powered off cpu state
target-arm: do not set do_interrupt handler for AArch64 user mode
target-arm: add hvc and smc exception emulation handling
infrastructure
target-arm: add emulation of PSCI calls for system emulation
arm/virt: enable PSCI emulation support for system emulation
hw/arm/virt.c | 70 +++++++++----------
target-arm/Makefile.objs | 1 +
target-arm/cpu-qom.h | 11 +++
target-arm/cpu.c | 17 +++--
target-arm/cpu.h | 8 +++
target-arm/cpu64.c | 2 +
target-arm/helper-a64.c | 19 +++++
target-arm/helper.c | 35 ++++++++++
target-arm/internals.h | 20 ++++++
target-arm/kvm-consts.h | 40 +++++++++++
target-arm/machine.c | 5 +-
target-arm/psci.c | 171 +++++++++++++++++++++++++++++++++++++++++++++
target-arm/translate-a64.c | 26 ++++---
target-arm/translate.c | 24 +++++--
14 files changed, 391 insertions(+), 58 deletions(-)
create mode 100644 target-arm/psci.c
--
1.8.3.2
