On 10 October 2014 13:22, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 10 October 2014 12:02, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote: >> On 10 October 2014 12:56, Peter Maydell <peter.mayd...@linaro.org> wrote: >>> Do you see the odd behaviour after guest reset for 32 >>> bit SMP cores? >>> >> >> I will try to reproduce it. I haven't tried, and I wasn't aware that >> SMP on TCG is supposed to be stable now otherwise. > > It has always been *supposed* to be stable, the only reason > we didn't have it enabled on the AArch64 virt board was > that we didn't have PSCI implemented. There were some > bugs that we fixed recently. Anything else obviously needs > to be reported as a bug and investigated so we can fix it... > > (32 bit TCG SMP support on boards like vexpress has been > supported for a long time. It just doesn't often make > much practical sense to use an SMP config because it will > inevitably be slower than the single-CPU config.) >
OK >>>> However, we still haven't addressed the CPU reset case, so issuing the >>>> PSCI reset under -bios does nothing. > >>> Yep, that's also on my todo list, but it's orthogonal to >>> this patch series. We probably want this variant, though, >>> right? >>> >>> http://marc.info/?l=qemu-devel&m=141099155616120&w=2 >> >> Yes, you're right, I had forgotten about sending that out. > > Can I get you to send out that as a proper patch then, > please? > Of course. -- Ard.
