Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c| 22 ++
tests/data/acpi/aarch64/virt/APIC.its_off | Bin 0 -> 184 bytes
tests/data/acpi/aarch64/virt/FACP.its_off | Bin 0 -> 276 bytes
tests/data/acpi/aarch64/virt/IORT.its_off | Bin 0 -> 23
Cc'ing Jim & Frank
On 18/3/25 22:31, Richard Henderson wrote:
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel
Hi ewanhai,
On 3/30/25 8:55 PM, ewanhai wrote:
> Hi Dongli,
>
[snip]
>
> [2] As mentioned in [1], QEMU always sets the vCPU's vendor to match the
> host's
> vendor
> when acceleration (KVM or HVF) is enabled. Therefore, if users want to
> emulate a
> Zhaoxin CPU on an Intel host, the vendor
+Stefan
On 29/3/25 16:43, BALATON Zoltan wrote:
We have several device tree files already and may have more in the
future so add a new dtb subdirectory and move device tree files there
so they are not mixed with ROM binaries.
Signed-off-by: BALATON Zoltan
---
MAINTAINERS
John Snow writes:
> On Fri, Mar 28, 2025 at 4:36 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Well, I tried. Maybe not very hard. Sorry!
>>
>> No need to be sorry! Kick-starting discussion with limited effort is
>> better than a big effort going into a direction that turns out to
Hi Pierrick,
On 1/4/25 01:42, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver is missing.
Per commit 903e870f245 ("plugins/api: split out binary
path/start/end/entry code") this is deliberate:
The BSD user-mod
From: Bernhard Beschow
TYPE_FSL_IMX8MP is created using object_new(), so must be realized with
qdev_realize_and_unref() to keep the reference counting intact.
Fixes: a4eefc69b237 "hw/arm: Add i.MX 8M Plus EVK board"
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Message-ID: <202503
From: Zheng Huang
Fix a memory leak bug in ufs_init_pci() due to u->irq
not being freed in ufs_exit().
Signed-off-by: Zheng Huang
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <43ceb427-87aa-44ee-9007-dbaecc499...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ufs/ufs.c | 3 +++
1
All these devices are part of SoC components and can not
be created manually.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250325224310.8785-9-phi...@linaro.org>
---
hw/misc/bcm2835_cprman.c | 8
hw/misc/npcm_clk.c | 6 ++
hw/misc/stm32l4x5_rc
On Tue, Mar 18, 2025 at 03:56:24PM +, Jonathan Cameron wrote:
> On Mon, 17 Mar 2025 16:31:29 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section
> > 7.6.7.6.1
> >
> > Signed-off-by: Anisa Su
> > --- a/hw/c
From: Richard Henderson
When update_pagemask was split from helper_mtc0_pagemask,
we failed to actually write to the new parameter but continue
to write to env->CP0_PageMask. Thus the use within
page_table_walk_refill modifies cpu state and not the local
variable as expected.
Simplify by renami
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250325224310.8785-5-phi...@linaro.org>
---
hw/dma/i82374.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c
index 9652d47adcd..0bf69ef399b 100644
--- a/hw/dma/i82374.c
+++ b/hw/dm
Fix copy/paste error writing to the ATU_UPPER_TARGET
register, we want to update the upper 32 bits.
Cc: qemu-sta...@nongnu.org
Reported-by: Joey
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861
Fixes: d64e5eabc4c ("pci: Add support for Designware IP block")
Signed-off-by: Philippe Mat
On Mon Mar 31, 2025 at 11:25 PM AEST, Corey Minyard wrote:
> On Mon, Mar 31, 2025 at 10:57:24PM +1000, Nicholas Piggin wrote:
>> Linux issues this command when booting a powernv machine.
>
> This is good, just a couple of nits.
>
>>
>> Signed-off-by: Nicholas Piggin
>> ---
>> include/hw/ipmi/ipm
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver is missing.
Signed-off-by: Pierrick Bouvier
---
bsd-user/main.c | 12
1 file changed, 12 insertions(+)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index fdb160bed0f..329bd1acc
All MemoryRegionOps::read/write() handlers switch over a 32-bit
aligned value, because converted using TO_REG(), which is defined
as:
#define TO_REG(offset) ((offset) >> 2)
So all implementations are 32-bit.
Set min/max access_size accordingly.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mi
Hi Joel,
On 19/11/24 11:29, Peter Maydell wrote:
On Tue, 19 Nov 2024 at 02:53, Joel Stanley wrote:
On Mon, 18 Nov 2024 at 20:40, Peter Maydell wrote:
Have you reviewed all the device read/write function
implementations for these devices to check whether
(a) changing the .valid value does th
Mark SCU MemoryRegionOps read/write handler implementations
as 32-bit, then allow down to 8-bit accesses.
Joel Stanley (1):
hw/misc/aspeed_scu: Correct minimum access size for AST2500 / AST2600
Philippe Mathieu-Daudé (1):
hw/misc/aspeed_scu: Set MemoryRegionOps::impl::access_size to 32-bit
From: Zheng Huang
Fix a memory leak bug in sdhci_pci_realize() due to s->irq
not being freed in sdhci_pci_exit().
Signed-off-by: Zheng Huang
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <09ddf42b-a6db-42d5-954b-148d09d8d...@gmail.com>
[PMD: Moved qemu_free_irq() call before sdhci_common_unr
From: Bernhard Beschow
The SoC has three SPI controllers, not four.
Remove the extra define of an SPI IRQ.
Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers"
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-ID: <20250318205709.28862-4-shen...@gmail.com>
Signed-off-b
Prasad Pandit writes:
> From: Prasad Pandit
>
> Hello,
>
> * This series (v8) splits earlier patch-2 which enabled multifd and
> postcopy options together into two separate patches. One modifies
> the channel discovery in migration_ioc_process_incoming() function,
> and second one enables
[2] As mentioned in [1], QEMU always sets the vCPU's vendor to match the host's
vendor
when acceleration (KVM or HVF) is enabled. Therefore, if users want to emulate a
Zhaoxin CPU on an Intel host, the vendor must be set manually.Furthermore,
should we display a warning to users who enable both vP
On 1/4/25 06:15, Joel Stanley wrote:
In commit 8fd2518ef2f8 ("hw: Centralize handling of -machine dumpdtb
option") the call to dump was moved with respect to the init of the
machine. This resulted in the device tree missing parts of the machine
description, depending on how they construct their
John Snow writes:
> On Thu, Mar 27, 2025 at 5:11 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > This patch changes the qapidoc transmogrifier to generate Return value
>> > documentation for any command that has a return value but hasn't
>> > explicitly documented that return value.
On 3/31/25 10:54, Nicholas Piggin wrote:
I've been struggling with these couple of performance issues with
TB coherency. I almost thought deferring flush to icbi would be
workable, buta note in the docs says that exceptions require TB
to be coherent... I don't know what requires that, maybe it co
When the cache-controller feature is not implemented,
log potential ASI access as unimplemented.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Clément Chigot
Message-Id: <20250325123927.74939-4-phi...@linaro.org>
---
target/sparc/ldst_helper.c | 6 ++
1 file changed, 6 insertions(+)
d
This device is part of SoC components thus can not
be created manually.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250325224310.8785-10-phi...@linaro.org>
---
hw/nvram/xlnx-efuse.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/nvram/xlnx-efuse.c b/h
From: Chung-Yi Chen
Fix a misconfiguration issue in the read implementation of the
AUX_MU_IIR_REG register. This issue can lead to a transmit interrupt
being incorrectly interpreted as a receive interrupt when the receive
interrupt is disabled and the receive FIFO holds valid bytes.
The AUX_MU_I
On 3/31/25 10:54, Nicholas Piggin wrote:
Add an option TARGET_HAS_LAZY_ICACHE that does not invalidate TBs upon
store, but instead tracks that the icache has become incoherent, and
provides a tb_flush_incoherent() function that the target may call to
bring the TB back to coherency.
We're not go
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250325224310.8785-4-phi...@linaro.org>
---
hw/display/dm163.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
index 75a91f62bd3..f6f0ec0c632 100644
--- a/hw/d
From: Thomas Huth
We are not aware of anybody still using this machine, support for it
has been withdrawn from the Linux kernel (i.e. there also won't be
any future development anymore), and we are not aware of any binaries
online that could be used for regression testing to avoid that the
machin
On Mon Mar 31, 2025 at 11:13 PM AEST, Corey Minyard wrote:
> On Mon, Mar 31, 2025 at 10:57:22PM +1000, Nicholas Piggin wrote:
>> If the dont-log flag is set in the 'timer use' field for the
>> 'set watchdog' command, a watchdog timeout will not get logged as
>> a timer use expiration.
>>
>> Signed
On Mon, Mar 31, 2025 at 06:03:11PM -0500, Corey Minyard wrote:
> On Tue, Apr 01, 2025 at 08:37:19AM +1000, Nicholas Piggin wrote:
> > On Mon Mar 31, 2025 at 11:13 PM AEST, Corey Minyard wrote:
> > > On Mon, Mar 31, 2025 at 10:57:22PM +1000, Nicholas Piggin wrote:
> > >> If the dont-log flag is set
In commit 8fd2518ef2f8 ("hw: Centralize handling of -machine dumpdtb
option") the call to dump was moved with respect to the init of the
machine. This resulted in the device tree missing parts of the machine
description, depending on how they construct their device tree.
The arm virt machine is m
From: Bernhard Beschow
Deriving from TYPE_SYS_BUS_DEVICE fixes the SoC object to be reset upon machine
reset. It also makes the SoC implementation not user-creatable which can trigger
the following crash:
$ ./qemu-system-aarch64 -M virt -device fsl-imx8mp
**
ERROR:../../devel/qemu/tcg/tcg
On 3/18/25 14:31, Richard Henderson wrote:
Split out mmap_lock, et al from page-protection.h
to a new header.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
This breaks bsd-user which needs some extra includes as well.
See here for details and a patch fixing it [1] (also att
On 3/31/25 15:05, Pierrick Bouvier wrote:
On 3/18/25 14:31, Richard Henderson wrote:
Split out mmap_lock, et al from page-protection.h
to a new header.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
This breaks bsd-user which needs some extra includes as well.
See here for
On Tue, 2025-04-01 at 01:04 +0200, Philippe Mathieu-Daudé wrote:
> From: Joel Stanley
>
> Guest code was performing a byte load to the SCU MMIO region, leading
> to the guest code crashing (it should be using proper accessors, but
> that is not Qemu's bug). Hardware and the documentation[1] both
On 21/1/25 11:36, Thomas Huth wrote:
We are not aware of anybody still using this machine, support for it
has been withdrawn from the Linux kernel (i.e. there also won't be
any future development anymore), and we are not aware of any binaries
online that could be used for regression testing to av
From: Richard Henderson
Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing
the system page size because of what the Loongson kernel "prefers"
is flawed.
In the Loongson-2E manual, section 5.5, it is clear that the cpu
supports a 4k page size (along with many others). Similarly for
On Thu, Mar 27, 2025 at 1:36 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Wed, Mar 26, 2025 at 2:08 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > A few transitive dependencies were left floating; as a result, pip's
> >> > dependency solver can pull in newer d
On 3/24/25 23:58, Pierrick Bouvier wrote:
This series focuses on removing compilation units duplication in hw/arm. We
start with this architecture because it should not be too hard to transform it,
and should give us some good hints on the difficulties we'll meet later.
We first start by making
From: Richard Henderson
Match the prototype of cpu_memory_rw_debug().
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-Id: <20250325224403.4011975-4-richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/c
GIC ITS can be disabled using '-M its=off'.
When that occurs, it shouldn't be advertised in ACPI tables.
Philippe Mathieu-Daudé (5):
qtest/bios-tables-test: Add test for -M virt,its=off
qtest/bios-tables-test: Whitelist aarch64/virt/APIC.its_off blob
hw/arm/virt-acpi: Factor its_enabled() he
Changes in the tables:
@@ -1,32 +1,32 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240927 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembly of tests/data/acpi/aarch64/virt/APIC.its_off
*
* ACPI Data Table
Prepare for ACPI table change in aarch64/virt/APIC.its_off.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index d
On 3/18/25 14:31, Richard Henderson wrote:
Avoid testing CONFIG_USER_ONLY in semihost.h.
The only function that's required is semihosting_enabled.
Signed-off-by: Richard Henderson
This breaks bsd-user,
CONFIG_SEMIHOSTING is not defined in configs/targets/*bsd-user*, thus
the user stub is not
The initialization of 'has_architectural_pmu_version',
'num_architectural_pmu_gp_counters', and
'num_architectural_pmu_fixed_counters' is unrelated to the process of
building the CPUID.
Extract them out of kvm_x86_build_cpuid().
In addition, use cpuid_find_entry() instead of cpu_x86_cpuid(), beca
From: Zheng Huang
Address a memory leak bug in the usages of timer_del().
The issue arises from the incorrect use of the ambiguous timer API
timer_del(), which does not free the timer object. The LeakSanitizer
report this issue during fuzzing. The correct API timer_free() freed
the timer object
On Fri, 2025-03-28 at 12:06 -0700, Farhan Ali wrote:
> Starting with z15 (or newer) we can execute mmio
> instructions from userspace. On older platforms
> where we don't have these instructions available
> we can fallback to using system calls to access
> the PCI mapped resources.
>
> This patch
On 2025/3/31 17:44, Loïc Lefort wrote:
On Sat, Mar 29, 2025 at 10:03 AM LIU Zhiwei
wrote:
On 2025/3/14 03:30, Loïc Lefort wrote:
> Signed-off-by: Loïc Lefort
> Reviewed-by: Daniel Henrique Barboza
> ---
> target/riscv/pmp.c | 22 +++---
> 1 fil
On 29/3/25 12:30, Rakesh J wrote:
Thanks for feedback on [PATCH v1]!
I've posted v2 incorporating the suggestions:ve posted v2 incorporating
your suggestions
Paolo: You pointed out the size issue with .min_access_size = 1
and .max_access_size = 4, where bswap32 was wrong for 2-byte accesse
On 26/3/25 13:59, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
Last uses of ldtul_be_p() were removed in commit 78920b4ff2b
("target/sparc: Use explicit big-endian LD/ST API"), and of
ldtul_le_p() in 39631d57d7c ("target/riscv: Use explicit
little-endian LD/ST API"). Remove these legacy m
On Mon, Mar 31, 2025 at 6:39 AM Alex Bennée wrote:
> So what do people think? Where would be a good place for common test
> repository to live?
Maintaining the tests alongside the VIRTIO spec seems like a good fit
to me. Here is information on how to create a GitHub repo under the
OASIS VIRTIO Te
On 30/3/25 23:01, Rakesh Jeyasingh wrote:
pci_host_data_be_ops became unused after endianness fixes
Suggested-by: Paolo Bonzini
Signed-off-by: Rakesh Jeyasingh
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pci_host.c | 6 --
include/hw/pci-host/dino.h | 4
inclu
On 21/1/25 13:09, Jiaxun Yang wrote:
在2025年1月21日一月 下午12:07，Jiaxun Yang写道：
在2025年1月21日一月 上午10:36，Thomas Huth写道：
We are not aware of anybody still using this machine, support for it
has been withdrawn from the Linux kernel (i.e. there also won't be
any future development anymore), and we are no
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the big-core == 2xPnvCore scheme we moved to, this fix
uses the even PnvCore to store the scrach data.
Also remove a stray log message that came in wi
Commit 60d30cff847 ("target/ppc: Move SPR indirect registers into
PnvCore") was mismerged and moved the SPRs to power8-only, instead
of power9/10-only.
Fixes: 60d30cff847 ("target/ppc: Move SPR indirect registers into PnvCore")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Nicholas Piggin
---
target
On 31/3/25 14:03, Philippe Mathieu-Daudé wrote:
On 21/1/25 13:09, Jiaxun Yang wrote:
在2025年1月21日一月 下午12:07，Jiaxun Yang写道：
在2025年1月21日一月 上午10:36，Thomas Huth写道：
We are not aware of anybody still using this machine, support for it
has been withdrawn from the Linux kernel (i.e. there also won't be
Linux issues this command when booting a powernv machine.
Signed-off-by: Nicholas Piggin
---
include/hw/ipmi/ipmi.h | 14 +++
hw/ipmi/ipmi_bmc_sim.c | 56 --
hw/ipmi/ipmi_bt.c | 2 ++
hw/ipmi/ipmi_kcs.c | 1 +
4 files changed, 71 inserti
On Sun, 23 Mar 2025, Christian Schoenebeck wrote:
On Sunday, March 16, 2025 1:20:46 AM CET BALATON Zoltan wrote:
Quoting Volker Rümelin: "try-poll=on tells the ALSA backend to try to
use an event loop instead of the audio timer. This works most of the
time. But the poll event handler in the ALSA
Clearing the physical thread enable register should reset the
TCTX state and reject accesses to it. xive currently does not
model this.
skiboot firmware uses this register to reset the XIVE TIMA state
(see xive_reset_enable_thread()), which can be in an arbitrary state
e.g., when called by OPAL_XI
Bring gdb's physical memory access handling up to speed with the CPU
memory access, by setting MemTxAttribute.debug=1, and by checking for
memory transaction errors.
GDB with PhyMemMode will now report failure for memory access outside
valid system memory addresses, and it is also able to write to
Debugger-driven invalid memory accesses are not guest errors, so should
not cause these error logs.
Debuggers can access memory wildly, including access to addresses not
specified by the user (e.g., gdb it might try to walk the stack or load
target addresses to display disassembly). Failure is rep
This adds .debug=1 attribute for GDB's phys mem access mode, adds
memory transaction error handling for it so it reports cannot access
memory instead of silent success, and silences warning logs for
invalid memory access coming from the debugger.
Changes since v1:
- Move phys_memory_rw_debug() int
On Fri, Mar 28, 2025 at 12:06:26PM -0700, Farhan Ali wrote:
> Add a generic QEMU API for PCI MMIO reads/writes.
> The functions access little endian memory and returns
> the result in host cpu endianness.
>
> Signed-off-by: Farhan Ali
> ---
> include/qemu/pci-mmio.h | 116 +++
Hi,
This patch adds a cleanup operation for 9p-synth, which fixes a memory
leak bug in synth_init() and other related operations. All child nodes
of synth_root need to be freed before the entire filesystem exits.
If you have any better ideas for the implementation, please feel free
to share them.
Register Control-Program Identification data with the live
migration infrastructure.
Signed-off-by: Shalini Chellathurai Saroja
Reviewed-by: Nina Schoetterl-Glausch
---
hw/s390x/sclpcpi.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/hw/s390x/sclpcpi.c b/hw/s3
Add Control-Program Identification data to the QEMU Object
Model (QOM), along with the timestamp in which the data was received.
Example:
virsh # qemu-monitor-command vm --pretty '{
"execute": "qom-get",
"arguments": {
"path": "/machine/sclp/s390-sclp-event-facility/sclpcpi",
"property": "control-
On 21/3/25 23:12, Heinrich Schuchardt wrote:
Currently resetting the leads to resynchronizing the Goldfish RTC with the
system clock of the host. In real hardware an RTC reset would not change
the wall time. Other RTCs like pl031 do not show this behavior.
Move the synchronization of the RTC wit
On 28/3/25 18:55, Richard Henderson wrote:
Richard Henderson (3):
target/mips: Revert TARGET_PAGE_BITS_VARY
target/mips: Require even maskbits in update_pagemask
target/mips: Simplify and fix update_pagemask
Series queued, thanks!
On 25/3/25 23:42, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (12):
hw/block/m25p80: Categorize and add description
hw/display/dm163: Add description
hw/dma/i82374: Categorize and add description
hw/misc/pll: Do not expose as user-creatable
hw/nvram/xlnx-efuse: Do n
PPC CPU has TYPE_INTERRUPT_STATS_PROVIDER interface but it does not
implement the print_info function. This causes 'info pic' to print
a line like:
Interrupt controller information not available for
power10_v2.0-powerpc64-cpu.
Add a print_info panel for CPUs with irq delivery status.
Sig
The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
The correct value is 0x5b. This mistake occurred because the extended
model bits in cpuid[eax=0x1].eax were overlooked, and only the base
model was used.
This patch corrects the model field.
Signed-off-by: Ewan Hai
---
targe
On 3/14/2025 6:23 PM, Chenyi Qiang wrote:
>
>
> On 3/14/2025 5:50 PM, David Hildenbrand wrote:
>> On 14.03.25 10:30, Chenyi Qiang wrote:
>>>
>>>
>>> On 3/14/2025 5:00 PM, David Hildenbrand wrote:
On 14.03.25 09:21, Chenyi Qiang wrote:
> Hi David & Alexey,
Hi,
>
On Sat, Mar 29, 2025 at 10:03 AM LIU Zhiwei
wrote:
>
> On 2025/3/14 03:30, Loïc Lefort wrote:
> > Signed-off-by: Loïc Lefort
> > Reviewed-by: Daniel Henrique Barboza
> > ---
> > target/riscv/pmp.c | 22 +++---
> > 1 file changed, 15 insertions(+), 7 deletions(-)
> >
> > diff
On Sun, Mar 30, 2025 at 10:58:57PM +0200, Bernhard Beschow wrote:
> Now that there is logging support in Rust for QEMU, use it in the pl011
> device.
>
> Signed-off-by: Bernhard Beschow
> ---
> rust/hw/char/pl011/src/device.rs | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
On 3/30/25 22:58, Bernhard Beschow wrote:
A qemu_log_mask!() macro is provided which expects similar arguments as the C
version. However, the formatting works as one would expect from Rust.
To maximize code reuse the macro is just a thin wrapper around qemu_log().
Also, just the bare minimum of
Prasad Pandit writes:
> From: Prasad Pandit
>
> Enable Multifd and Postcopy migration together.
> The migration_ioc_process_incoming() routine
> checks magic value sent on each channel and
> helps to properly setup multifd and postcopy
> channels.
>
> The Precopy and Multifd threads work during
These little things came up when looking at behaviour of IPMI with
the bmc-sim implementation running the ppc powernv machine, and
trying to clean up error messages and missing features.
Thanks,
Nick
Nicholas Piggin (3):
ipmi/bmc-sim: implement watchdog dont log flag
ipmi/bmc-sim: add error h
Prasad Pandit writes:
> From: Peter Xu
>
> Implement save_postcopy_prepare(), preparing for the enablement of both
> multifd and postcopy.
>
> Please see the rich comment for the rationals.
>
> Signed-off-by: Peter Xu
> Signed-off-by: Prasad Pandit
> ---
> migration/ram.c | 37 +++
Prefer the safer (less bug-prone) deposit/extract API
to access lower/upper 32-bit of 64-bit registers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/designware.c | 47 ++--
1 file changed, 16 insertions(+), 31 deletions(-)
diff --git a/hw/pci-host/de
Add an option TARGET_HAS_LAZY_ICACHE that does not invalidate TBs upon
store, but instead tracks that the icache has become incoherent, and
provides a tb_flush_incoherent() function that the target may call to
bring the TB back to coherency.
XXX: docs/devel/tcg.rst says that this is not permitted
Fixed translations (mapping and protections unchanged) do not have
to restrict TB chaining to within a target page.
Hypervisor-real mode is a fixed translation.
TODO: Supervisor-real mode in spapr should also be a fixed translation.
---
target/ppc/translate.c | 20
1 file ch
I've been struggling with these couple of performance issues with
TB coherency. I almost thought deferring flush to icbi would be
workable, buta note in the docs says that exceptions require TB
to be coherent... I don't know what requires that, maybe it could
be worked around?
Another thing is Pow
On Fri, Mar 28, 2025 at 12:06:27PM -0700, Farhan Ali wrote:
> Use the QEMU PCI MMIO functions to read/write
> to NVMe registers, rather than directly accessing
> them.
>
> Signed-off-by: Farhan Ali
> ---
> block/nvme.c | 37 +
> 1 file changed, 21 insertions(+
Hi Phil,
On 3/31/25 12:20, Philippe Mathieu-Daudé wrote:
Prefer the safer (less bug-prone) deposit/extract API
to access lower/upper 32-bit of 64-bit registers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/designware.c | 47 ++--
1 file changed,
On 28/3/25 04:21, Zheng Huang wrote:
Hi,
This patch addresses a memory leak bug in the usages of `timer_del()`.
The issue arisesfrom the incorrect use of the ambiguous timer API
`timer_del()`, which does not free the timer object. The LeakSanitizer
report this issue during fuzzing. The correct AP
On 28/3/25 13:37, Chung-Yi Chen wrote:
This patch fixes a misconfiguration issue in the read implementation of
the AUX_MU_IIR_REG register. This issue can lead to a transmit interrupt
being incorrectly interpreted as a receive interrupt when the receive
interrupt is disabled and the receive FIFO
On 29/3/25 12:47, Zheng Huang wrote:
Hi,
This patch fixes a memory leak bug in `ufs_init_pci()`. `u->irq` is
not freed in `ufs_exit()`.
Signed-off-by: Zheng Huang
---
hw/ufs/ufs.c | 3 +++
1 file changed, 3 insertions(+)
Queued to hw-misc, thanks!
Stefan Hajnoczi writes:
> On Mon, Mar 31, 2025 at 6:39 AM Alex Bennée wrote:
>> The unikernel utilizes rcore-os's no_std VirtIO drivers to discover and
>> initialize a range of VirtIO devices.
>
> https://github.com/rcore-os/virtio-drivers
>
> I noticed that VIRTIO_F_VERSION_1, VIRTIO_F_RING_PAC
On 28/3/25 18:55, Richard Henderson wrote:
Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing
the system page size because of what the Loongson kernel "prefers"
is flawed.
In the Loongson-2E manual, section 5.5, it is clear that the cpu
supports a 4k page size (along with many other
On 21/03/2025 11:22, Cédric Le Goater wrote:
> On 3/19/25 13:21, Joao Martins wrote:
>> On 18/03/2025 09:54, Cédric Le Goater wrote:
>>> Rename these routines :
>>>
>>> vfio_devices_all_device_dirty_tracking_started ->
>>> vfio_dirty_tracking_devices_is_started_all
>>> vfio_devices_all_dirty_
On 28/3/25 18:55, Richard Henderson wrote:
The number of bits set in PageMask must be even.
Fixes: d40b55bc1b86 ("target/mips: Fix PageMask with variable page size")
Signed-off-by: Richard Henderson
---
target/mips/tcg/system/cp0_helper.c | 23 ---
1 file changed, 8 inser
On 28/3/25 18:55, Richard Henderson wrote:
When update_pagemask was split from helper_mtc0_pagemask,
we failed to actually write to the new parameter but continue
to write to env->CP0_PageMask. Thus the use within
page_table_walk_refill modifies cpu state and not the local
variable as expected.
On 28/3/25 10:49, Zheng Huang wrote:
Hi,
This patch fixes a memory leak bug in `sdhci_pci_realize()`. `s->irq` is
not freed in `sdhci_pci_exit()`.
Signed-off-by: Zheng Huang
---
hw/sd/sdhci-pci.c | 2 ++
1 file changed, 2 insertions(+)
Queued to hw-misc, thanks!
On 30/3/25 23:10, Aditya Gupta wrote:
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Newer skiboot might not be able to boot Power8NVL since skiboot v7.0
Deprecate the 8E and 8NVL variants.
After deprecation, QEMU will print a warning like belo
On 25/03/30 10:24AM, Philippe Mathieu-Daudé wrote:
> On 29/3/25 19:04, Aditya Gupta wrote:
> > <...snip...>
> >
> > +if (_deprecation_note) {
> > \
> > +cc->deprecation_note = _deprecation_note;
> > \
>
> As men
On 31/3/25 14:03, Nicholas Piggin wrote:
Commit 60d30cff847 ("target/ppc: Move SPR indirect registers into
PnvCore") was mismerged and moved the SPRs to power8-only, instead
of power9/10-only.
Fixes: 60d30cff847 ("target/ppc: Move SPR indirect registers into PnvCore")
Cc: qemu-sta...@nongnu.org
On Mon, Mar 31, 2025 at 07:52:33AM -0400, Stefan Hajnoczi wrote:
> On Mon, Mar 31, 2025 at 6:39 AM Alex Bennée wrote:
> > So what do people think? Where would be a good place for common test
> > repository to live?
>
> Maintaining the tests alongside the VIRTIO spec seems like a good fit
> to me.
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