I've been struggling with these couple of performance issues with
TB coherency. I almost thought deferring flush to icbi would be
workable, buta note in the docs says that exceptions require TB
to be coherent... I don't know what requires that, maybe it could
be worked around?
Another thing is PowerVM runtime firmware runs with MMU disabled
for ifetch. This means a fixed linear map with no memory protection.
Is it possible we can enable goto tb across TARGET_PAGE_SIZE for
ifetches in this mode?
Thanks,
Nick
Nicholas Piggin (3):
accel/tcg: Option to permit incoherent translation block cache vs
stores
target/ppc: define TARGET_HAS_LAZY_ICACHE
target/ppc: Allow goto-tb on fixed real mode translations
accel/tcg/tb-internal.h | 10 ++++++
include/exec/tb-flush.h | 3 ++
target/ppc/cpu.h | 16 +++++++++
accel/tcg/cputlb.c | 15 +++++++--
accel/tcg/tb-maint.c | 73 ++++++++++++++++++++++++++++++++++++++++
target/ppc/mem_helper.c | 2 ++
target/ppc/translate.c | 21 ++++++++++++
system/memory_ldst.c.inc | 2 +-
8 files changed, 138 insertions(+), 4 deletions(-)
--
2.47.1
