On 3/31/25 10:54, Nicholas Piggin wrote:
I've been struggling with these couple of performance issues with TB coherency. I almost thought deferring flush to icbi would be workable, buta note in the docs says that exceptions require TB to be coherent... I don't know what requires that, maybe it could be worked around?
Which note? Anyway, qemu implements accurate tb invalidation for x86 and s390x, which means we don't really need to do anything special for other targets.
Compare aarch64 "IC_IVAU" which (at least for system mode) is implemented as a nop.
Another thing is PowerVM runtime firmware runs with MMU disabled for ifetch. This means a fixed linear map with no memory protection. Is it possible we can enable goto tb across TARGET_PAGE_SIZE for ifetches in this mode?
No, there are several things that assume nothing jumps across TARGET_PAGE_SIZE, including breakpoints.
r~
