Hi ewanhai, On 3/30/25 8:55 PM, ewanhai wrote: > Hi Dongli, >
[snip] > > [2] As mentioned in [1], QEMU always sets the vCPU's vendor to match the > host's > vendor > when acceleration (KVM or HVF) is enabled. Therefore, if users want to > emulate a > Zhaoxin CPU on an Intel host, the vendor must be set manually.Furthermore, > should we display a warning to users who enable both vPMU and KVM acceleration > but do not manually set the guest vendor when it differs from the host vendor? Maybe not? Sometimes I emulate AMD on Intel host, while vendor is still the default :) >> I did many efforts, and I could not use Zhaoxin's PMU on Intel hypervisor. >> [snip] >> >> So far I am not able to use Zhaoxin PMU on Intel hypervisor. >> >> Since I don't have Zhaoxin environment, I am not sure about "vice versa". >> >> Unless there is more suggestion from Zhao, I may replace is_same_vendor() >> with >> vendor_compatible(). > I'm sorry I didn't provide you with enough information about the Zhaoxin PMU. > > 1. I made a mistake in the Zhaoxin YongFeng vCPU model patch. The correct > model > should be 0x5b, but I mistakenly set it to 0xb (11). The mistake happened > because > I overlooked the extended model bits from cpuid[eax=0x1].eax and only used the > base model. I'll send a fix patch soon. > > 2. As you can see in zhaoxin_pmu_init() in the Linux kernel, there is no > handling > for CPUs with family 0x7 and model (base + extended) 0x5b. The reason is > clear: > we submitted a patch for zhaoxin_pmu_init() to support YongFeng two years ago > (https://urldefense.com/v3/__https://lore.kernel.org/lkml/20230323024026.823-1- > silviazhao...@zhaoxin.com/__;!!ACWV5N9M2RV99hQ!NduXM- > ouGzo6_imecWUY_JxPGGp72W4M0Gk3ian- > na03t2R2BfTPwxnfNOS8JO1IGAL_F9G3ZnsY7zh2F7vuXAIS$ ), > but received no response. We will keep trying to resubmit it. > Thank you very much for explanation. The VM (v5.15) is able to detect PMU after the below is applied. diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b64ceaaba..9077c4c44f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5503,7 +5503,7 @@ static const X86CPUDefinition builtin_x86_defs[] = { .level = 0x1F, .vendor = CPUID_VENDOR_ZHAOXIN1, .family = 7, - .model = 11, + .model = 0x3b, .stepping = 3, /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ .features[FEAT_1_EDX] = I have changed model to 0x3b. [ 0.298541] smpboot: CPU0: Centaur Zhaoxin YongFeng Processor (family: 0x7, model: 0x3b, stepping: 0x3) [ 0.299294] Performance Events: [ 0.299295] core: Welcome to zhaoxin pmu! [ 0.300176] core: Version check pass! [ 0.301002] ZXE events, zhaoxin PMU driver. [ 0.301177] ... version: 2 [ 0.302061] ... bit width: 48 [ 0.302174] ... generic registers: 4 [ 0.303053] ... value mask: 0000ffffffffffff [ 0.303174] ... max period: 00007fffffffffff [ 0.304174] ... fixed-purpose events: 3 [ 0.305063] ... event mask: 000000070000000f In the v3 patchset, it always follows the Intel path, if both guest and host are Intel or Zhaoxin. https://lore.kernel.org/qemu-devel/20250331013307.11937-9-dongli.zh...@oracle.com/ Thank you very much! Dongli Zhang
