Re: [PATCH] hw/ufs: free irq on exit

On 29/3/25 12:47, Zheng Huang wrote: Hi, This patch fixes a memory leak bug in `ufs_init_pci()`. `u->irq` is not freed in `ufs_exit()`. Signed-off-by: Zheng Huang --- hw/ufs/ufs.c | 3 +++ 1 file changed, 3 insertions(+) Reviewed-by: Philippe Mathieu-Daudé

[PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register

From: Anton Blanchard Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--- 1 file changed, 26 inser

Re: [PATCH v2 01/11] include/exec: fix assert in size_memop

On 2025/03/24 19:21, Alex Bennée wrote: We can handle larger sized memops now, expand the range of the assert. Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits) Signed-off-by: Alex Bennée --- v2 - instead of 128 use 1 << MO_SIZE for future proofing --- include/exec/memop.h | 4 ++-- 1 fi

Re: [PATCH v2 5/5] target/riscv: pmp: remove redundant check in pmp_is_locked

On 2025/3/14 03:30, Loïc Lefort wrote: Remove useless check in pmp_is_locked, the function will return 0 in either case. Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Zhiwei --- target/riscv/pmp.c | 5 - 1 file changed, 5 deletions(-) diff

Re: [PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function

On 2025/3/14 03:30, Loïc Lefort wrote: Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Zhiwei --- target/riscv/pmp.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/

Re: [PATCH] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

On 28/3/25 18:34, Paolo Bonzini wrote: On Fri, Mar 28, 2025 at 3:16 PM BALATON Zoltan wrote: It should be fine. You should take into account: - the endianness produced by pci_data_read/pci_data_write (always little endian) - the endianness expected by the guest (big endian under the conditio

Re: [PATCH] hw/acpi: Remove legacy reset handling from vmclock

On Fri, 2025-02-07 at 14:34 +, David Woodhouse wrote: > From: David Woodhouse > > The vmclock device only has a reset method in order to plug its memory > region into the system memory. It was originally done this way in order > to defer the memory_region_add_subregion_overlap() from vmclock_

Re: [PATCH v2 2/3] include: Add a header to define PCI MMIO functions

On 29/3/25 07:03, Farhan Ali wrote: On 3/28/2025 1:44 PM, Philippe Mathieu-Daudé wrote: On 28/3/25 20:06, Farhan Ali wrote: Add a generic QEMU API for PCI MMIO reads/writes. The functions access little endian memory and returns the result in host cpu endianness. Signed-off-by: Farhan Ali ---

Re: [PATCH v2 04/11] gdbstub: introduce target independent gdb register helper

On 2025/03/24 19:21, Alex Bennée wrote: The current helper.h functions rely on hard coded assumptions about target endianess to use the tswap macros. We also end up double swapping a bunch of values if the target can run in multiple endianess modes. Avoid this by getting the target to pass the en

Re: [PATCH v2 3/5] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode

On 2025/3/14 03:30, Loïc Lefort wrote: With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg writes would match the wrong cases of Smepmp truth table. The existing code allows writes for the following cases: - L=1, X=0: cases 8, 10, 12, 14 - L=0, RWX!=WX: cases 0-2, 4-

Re: [PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed

On 2025/3/14 03:30, Loïc Lefort wrote: Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza --- target/riscv/pmp.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c5f6cdaccb..845915e0c8 100

[PATCH 2/2] pc-bios: Move device tree files in their own subdir

We have several device tree files already and may have more in the future so add a new dtb subdirectory and move device tree files there so they are not mixed with ROM binaries. Signed-off-by: BALATON Zoltan --- MAINTAINERS| 2 +- pc-bios/{ => dtb}/bamboo.dtb

[PATCH v2] target/ppc: Deprecate Power8E and Power8NVL

Power8E and Power8NVL variants are not of much use in QEMU now, and not being maintained either. Newer skiboot might not be able to boot Power8NVL since skiboot v7.0 Deprecate the 8E and 8NVL variants. After deprecation, QEMU will print a warning like below when the CPU/Chips are used: $ ./

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

Hi Rakesh, On 29/3/25 01:49, rakeshj wrote: The GT-64120 PCI controller requires special handling where: 1. Host bridge (device 0) must use native endianness 2. Other devices follow MByteSwap bit in GT_PCI0_CMD Previous implementation accidentally swapped all accesses, breaking host bridge dete

[PATCH] hw/ufs: free irq on exit

Hi, This patch fixes a memory leak bug in `ufs_init_pci()`. `u->irq` is not freed in `ufs_exit()`. Signed-off-by: Zheng Huang --- hw/ufs/ufs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 1ccd6f88b6..e80e065fea 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/

Re: [PATCH v2 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges

On 2025/3/14 03:30, Loïc Lefort wrote: When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs but should not affect interpretation of actual PMP rules. This is not the case with the current implementation where pmp_hart_has_privs calls pmp_is_locked which implements mse

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

On Sat, 29 Mar 2025, Philippe Mathieu-Daudé wrote: Hi Rakesh, On 29/3/25 01:49, rakeshj wrote: The GT-64120 PCI controller requires special handling where: 1. Host bridge (device 0) must use native endianness 2. Other devices follow MByteSwap bit in GT_PCI0_CMD Previous implementation accident

Re: [PATCH] target/ppc: Deprecate Power8E and Power8NVL

On 25/03/28 08:23AM, Cédric Le Goater wrote: > On 3/28/25 05:06, Aditya Gupta wrote: > > Power8E and Power8NVL variants are not of much use in QEMU now, and not > > being maintained either. > > > > Deprecate the 8E and 8NVL variants. > > > > After deprecation, QEMU will print a warning like below

[PATCH v2 00/12] Fix RVV encoding corner cases

This patch series fixes several corner cases of RISC-V vector instruction's encoding constraints. Building on Anton's original work, this v2 series specifically addresses: 1. Illegal overlaps between source registers 2. Corner cases in complex vector instructions like vrgatherei16 3. Handling of

[PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c

[PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.in

[PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

From: Anton Blanchard Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc ind

[PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.in

[PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector mask-register logical instructions with vm=0 are reserved. Signed-off-by: Max Chou --- target/riscv/insn32.decode | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/

[PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)

Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvbf16.c.inc | 9 ++- target/riscv/insn_t

[PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

Handle the overlap of source registers with different EEWs. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/ins

[PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.in

[PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/i

[PATCH 1/2] system/datadir: Add new type constant for DTB files

Currently DTB files are mixed with ROMs under BIOS type. Separate them under a new type constant and turn defines into an enum while at it. Signed-off-by: BALATON Zoltan --- hw/microblaze/boot.c | 2 +- hw/ppc/ppc440_bamboo.c | 2 +- hw/ppc/sam460ex.c | 2 +- hw/ppc/virtex_ml507.c |

[PATCH 0/2] Move device tree files in a subdir in pc-bios

Simple series doing what the subject says. BALATON Zoltan (2): system/datadir: Add new type constant for DTB files pc-bios: Move device tree files in their own subdir MAINTAINERS| 2 +- hw/microblaze/boot.c | 2 +- hw/ppc/ppc440_bambo

Re: [PATCH v2 04/11] gdbstub: introduce target independent gdb register helper

On 2025/03/24 19:32, Alex Bennée wrote: Alex Bennée writes: The current helper.h functions rely on hard coded assumptions about target endianess to use the tswap macros. We also end up double swapping a bunch of values if the target can run in multiple endianess modes. Avoid this by getting th

[PATCH v3] target/ppc: Deprecate Power8E and Power8NVL

Power8E and Power8NVL variants are not of much use in QEMU now, and not being maintained either. Newer skiboot might not be able to boot Power8NVL since skiboot v7.0 Deprecate the 8E and 8NVL variants. After deprecation, QEMU will print a warning like below when the CPU/Chips are used: $ ./

Re: [PATCH v2] target/ppc: Deprecate Power8E and Power8NVL

Hi Aditya, On 29/3/25 15:26, Aditya Gupta wrote: Power8E and Power8NVL variants are not of much use in QEMU now, and not being maintained either. Newer skiboot might not be able to boot Power8NVL since skiboot v7.0 Deprecate the 8E and 8NVL variants. After deprecation, QEMU will print a warni

Re: [PATCH] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

Thanks for feedback on [PATCH v1]! I've posted v2 incorporating the suggestions:ve posted v2 incorporating your suggestions Paolo: You pointed out the size issue with .min_access_size = 1 and .max_access_size = 4, where bswap32 was wrong for 2-byte accesses. I’ve fixed this with size-appropriate