[PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <ant...@tenstorrent.com>
Co-authored-by: Max Chou <max.c...@sifive.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index f397ae46446..728912fc1f2 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3660,7 +3660,9 @@ static bool int_ext_check(DisasContext *s, arg_rmr *a, 
uint8_t div)
         require_align(a->rd, s->lmul) &&
         require_align(a->rs2, s->lmul - div) &&
         require_vm(a->vm, a->rd) &&
-        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
+        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div) &&
+        vext_check_input_eew(s, -1, 0, a->rs2, s->sew, a->vm);
+
     return ret;
 }
 
-- 
2.43.0