This patch series fixes several corner cases of RISC-V vector
instruction's encoding constraints.
Building on Anton's original work, this v2 series specifically
addresses:
1. Illegal overlaps between source registers
2. Corner cases in complex vector instructions like vrgatherei16
3. Handling of register overlaps in vector widening/narrowing
instructions
4. Fix unmasked RVV instruction encoding (e.g. vcompress.vm)
Anton Blanchard (2):
target/riscv: rvv: Source vector registers cannot overlap mask
register
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
Max Chou (10):
target/riscv: Add vext_check_input_eew to check mismatched input EEWs
encoding constraint
target/riscv: rvv: Apply vext_check_input_eew to vector register
gather instructions
target/riscv: rvv: Apply vext_check_input_eew to
OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
target/riscv: rvv: Apply vext_check_input_eew to
OPIVV/OPFVV(vext_check_sss) instructions
target/riscv: rvv: Apply vext_check_input_eew to vector slide
instructions(OPIVI/OPIVX)
target/riscv: rvv: Apply vext_check_input_eew to vector integer
extension instructions(OPMVV)
target/riscv: rvv: Apply vext_check_input_eew to vector widen
instructions(OPMVV/OPMVX/etc.)
target/riscv: rvv: Apply vext_check_input_eew to vector narrow
instructions
target/riscv: rvv: Apply vext_check_input_eew to vector indexed
load/store instructions
target/riscv: Fix the rvv reserved encoding of unmasked instructions
target/riscv/insn32.decode | 18 +--
target/riscv/insn_trans/trans_rvbf16.c.inc | 9 +-
target/riscv/insn_trans/trans_rvv.c.inc | 167 +++++++++++++++++----
3 files changed, 154 insertions(+), 40 deletions(-)
--
2.43.0
