Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-5-phi...@linaro.org>
---
target/microblaze/cpu.c | 2 ++
1 file changed, 2 insert
Since commit 740b1759734 ("cpu-timers, icount: new modules")
we don't need to expose icount_align_option to all the
system code, we can restrict it to TCG. Since it is used as
a boolean, declare it as 'bool' type.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <
Ensure common code never use this target specific definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250305153929.43687-4-phi...@linaro.org>
---
include/exec/poison.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/poison.h b/include
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210133134.90879-3-phi...@linaro.org>
---
target/sparc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index dda811503b5..462bcb6c0e6 100644
---
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210133134.90879-2-phi...@linaro.org>
---
target/i386/cpu.h | 2 +-
target/i386/cpu.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 10c
Missed in commit b86f59c7155 ("accel: replace struct CpusAccel
with AccelOpsClass") which removed the single CpusAccel use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-7-phi...@linaro.org>
---
accel/kvm/kvm-cpus.h | 2 --
1 file changed
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-9-phi...@linaro.org>
---
target/sh4/cpu.c | 2 ++
1 file changed, 2 insertions(+)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250121142341.17001-5-phi...@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 7b6b22c431b..9dd6ac7c7
On 3/6/25 16:16, Andrey Drobyshev wrote:
On 3/5/25 11:19 PM, Steven Sistare wrote:
On 3/5/2025 11:50 AM, Andrey Drobyshev wrote:
On 3/4/25 9:05 PM, Steven Sistare wrote:
On 2/28/2025 1:37 PM, Andrey Drobyshev wrote:
On 2/28/25 8:35 PM, Andrey Drobyshev wrote:
On 2/28/25 8:20 PM, Steven Sista
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250121142341.17001-4-phi...@linaro.org>
---
target/tricore/cpu.h | 4
1 file changed, 4 insertions(+)
diff -
Simplify user implementation of cpu_memory_rw_debug() by
taking the mmap lock globally. See commit 87ab2704296
("linux-user: Allow gdbstub to ignore page protection")
for why this lock is necessary.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Hender
CPU_RESOLVING_TYPE is declared per target in "cpu.h". Include
it (along with "qom/object.h") to avoid when moving code around:
include/accel/accel-cpu-target.h:26:50: error: expected ')'
26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
|
get_float_exception_flags() returns exception flags,
which are distinct from the FPCR bits used as error code.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250211162604.83446-1-phi...@linaro.org>
---
target/alpha/fpu_helper.c | 15 +++
1 file c
Use GLib conversion macros to pass misa_mxl_max as
riscv_cpu_class_init() class data.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210133134.90879-6-phi...@linaro.org>
---
target/riscv/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(
Have the CPUClass::disas_set_info() callback always set\
the disassemble_info::endian field.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-7-phi...@linaro.org>
---
target/ppc/cpu_init.c | 2 ++
1 file changed, 2
Make XtensaConfigList::config not const. Only modify
XtensaConfig within xtensa_register_core(), when the
class is registered, not when it is initialized.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Max Filippov
Message-Id: <20250210133134.90879-4-phi...@linar
mo_endian() returns the target endianness, currently static.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241105130431.22564-16-phi...@linaro.org>
---
target/microblaze/translate.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-4-phi...@linaro.org>
---
target/arm/cpu.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
OpenRISC timer is architecturally tied to the CPU.
It doesn't belong to the machine init() code to
instanciate it: move its creation when a vCPU is
realized (after being created).
Reported-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20250114
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-10-phi...@linaro.org>
---
target/xtensa/cpu.c | 2 ++
1 file changed, 2 insertion
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for big-endian targets.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-3-phi...@linaro.org>
---
target/hppa/cpu.c | 1 +
targ
Slighly simplify cpu-target.c again by extracting cpu_exec_initfn()
to cpu-{system,user}.c, adding an empty stub for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-19-phi...@linaro.org>
---
cpu-target.c | 9
Fix style on code we are going to modify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-16-phi...@linaro.org>
---
cpu-target.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250210212931.62401-6-phi...@linaro.org>
---
target/mips/cpu.c | 10 +-
1 file changed, 5 ins
On 6/3/25 07:07, Aditya Gupta wrote:
Seems 'Asset' got missed in the documentation by mistake.
Also fix the one spellcheck issue pointed by spellcheck
Signed-off-by: Aditya Gupta
---
docs/devel/testing/functional.rst | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/
All CPUClass implementating disas_set_info() must set the
disassemble_info::endian value.
Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before
calling the CPUClass::disas_set_info() handler, then asserting
%endian is not BFD_ENDIAN_UNKNOWN after the call.
This allows removing the target_wo
CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7
("Use a dedicated function to request exit from execution
loop"), tlb_flush() and tb_flush() are related to TCG
accelerator.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-17-phi...@linar
This device is only used by the x86 targets, which are only
built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_LITTLE_ENDIAN (besides, the
DEVICE_BIG_ENDIAN case isn't tested). Simplify directly
using DEVICE_LITTLE_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé
Am 06.03.25 um 09:05 schrieb Thomas Huth:
QEMU does not support 32-bit Windows anymore, so we should not
tempt the users to download old builds.
OTOH, there is now interest in Windows build on arm computers instead
(see e.g.https://gitlab.com/qemu-project/qemu/-/issues/2850 ), so
let's add a lin
ping
On 9/1/25 13:54, Philippe Mathieu-Daudé wrote:
Hi Nick,
Ping? (series fully reviewed)
On 20/12/24 22:30, Philippe Mathieu-Daudé wrote:
Since v3:
- Addressed Nick & Harsh review comments
Remove the tswap() calls on ePAPR, and convert
them to big-endian LD/ST API on sPAPR.
Commit 35c653c4029 ("tcg: Add 128-bit guest memory
primitives") introduced the use of bswap128() which is
declared in "qemu/int128.h", commit de95016dfbf ("accel/tcg:
Implement helper_{ld,st}*_mmu for user-only") introduced the
other bswap*() uses, which are declared in "qemu/bswap.h".
Include the
On 6.03.2025 07:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls.
Seems like this patch subject/title is not aligned
well with its content, or a least incomplete.
Also, could you provide more detailed information
why TARGET_PAGE_SIZE is getting replaced by
qemu_target_page_si
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 3/6/25 07:28, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 02:45:52PM +0100, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 12:34:13PM +0100, Paolo Bonzini wrote:
Il gio 6 mar 2025, 10:27 Philippe M
From: "Maciej S. Szmigiero"
All callers to migration_incoming_state_destroy() other than
postcopy_ram_listen_thread() do this call with BQL held.
Since migration_incoming_state_destroy() ultimately calls "load_cleanup"
SaveVMHandlers and it will soon call BQL-sensitive code it makes sense
to alw
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241105130431.22564-17-phi...@linaro.org>
---
target/microblaze/cpu.h | 7 +++
target/microblaze/transl
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "22.2.1. Shadow Stack Pointer
(ssp) CSR access
On 2/28/25 21:25, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 2 ++
target/hexagon/gen_tcg_funcs.py | 32 +++-
2 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/ta
On 3/6/25 08:39, Peter Maydell wrote:
At the top of linux-user/aarch64/cpu_loop.c we define a set of
macros for reading and writing data and code words, but we never
use these macros. Delete them.
Signed-off-by: Peter Maydell
---
linux-user/aarch64/cpu_loop.c | 48 -
On 3/6/25 08:39, Peter Maydell wrote:
We would like to move arm_el_is_aa64() to internals.h; however, it is
used by access_secure_reg(). Make that function not be inline, so
that it can stay in cpu.h.
access_secure_reg() is used only in two places:
* in hflags.c
* in the user-mode arm emula
On 3/6/25 08:39, Peter Maydell wrote:
The arm_cpu_data_is_big_endian() and related functions are now used
only in target/arm; they can be moved to internals.h.
The motivation here is that we would like to move arm_current_el()
to internals.h.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Em Wed, 5 Mar 2025 02:21:26 +0100
Philippe Mathieu-Daudé escreveu:
> From: Gavin Shan
>
> acpi_ghes_memory_errors() is the only caller, no need to expose
> the function. Besides, the last 'return' in this function isn't
> necessary and remove it.
>
> No functional changes intended.
Please re
On 3/6/25 08:39, Peter Maydell wrote:
The functions arm_current_el() and arm_el_is_aa64() are used only in
target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that
query internal state of the CPU. Move them out of cpu.h and into
internals.h.
This means we need to include internals.h
On Fri, 7 Mar 2025 02:01:27 +0800
Tomita Moeko wrote:
> So far, IGD-specific quirks all require enabling legacy mode, which is
> toggled by assigning IGD to 00:02.0. However, some quirks, like the BDSM
> and GGC register quirks, should be applied to all supported IGD devices.
> A new config opti
On 3/6/25 08:39, Peter Maydell wrote:
+/* Return the effective value of SCR_EL3.RW */
+static inline bool arm_scr_rw_eff(CPUARMState *env)
+{
+/*
+ * SCR_EL3.RW has an effective value of 1 if:
+ * - we are NS and EL2 is implemented but doesn't support AArch32
+ * - we are S and
On 3/6/25 09:58, Philippe Mathieu-Daudé wrote:
On 6/3/25 17:23, Pierrick Bouvier wrote:
On 3/6/25 08:19, Richard Henderson wrote:
On 3/5/25 22:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/syndbg.c | 7 ---
hw/h
On 3/6/25 08:39, Peter Maydell wrote:
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
be RAO/WI. We don't enforce this. This isn't a problem yet because
at the moment all of our CPU types with AArch64 support AArch32 at
all exception levels, but in the future this is likely
Hi Maciej,
we are currently working toward building a single QEMU binary able to
emulate all architectures, and one prerequisite is to remove duplication
of compilation units (some are duplicated per target now, because of
compile time defines).
So the work here is to replace those compile t
On 06/03/2025 13.23, shalini wrote:
On 2025-03-05 16:56, Thomas Huth wrote:
On 24/02/2025 13.04, Shalini Chellathurai Saroja wrote:
Add Control-Program Identification (CPI) to the QEMU Object
Model (QOM). The CPI identifiers provide information about
the guest operating system. The CPI identifi
On Thursday, March 6, 2025 10:07:56 AM CET Greg Kurz wrote:
> On Tue, 4 Mar 2025 16:16:05 +0100
> Christian Schoenebeck wrote:
>
> > This function calls v9fs_co_close() and v9fs_co_closedir() in a loop. Each
> > one of the calls adds two thread hops (between main thread and a fs driver
> > backgr
The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm;
move their definitions to cpregs.h. There's no need to have them
defined in all the code that includes cpu.h.
Signed-off-by: Peter Maydell
---
target/arm/cpregs.h | 28
target/arm/cpu.h| 27
On 3/7/2025 12:22 AM, Zhao Liu wrote:
Hi Xiaoyao,
First, it's not a good practice that values in env->features[] cannot be
directly used for guest CPUID in void cpu_x86_cpuid(), but require further
adjustment there. env->features[] are supposed to be finalized at cpu
realization, so that after
We would like to move arm_el_is_aa64() to internals.h; however, it is
used by access_secure_reg(). Make that function not be inline, so
that it can stay in cpu.h.
access_secure_reg() is used only in two places:
* in hflags.c
* in the user-mode arm emulators, to decide whether to store
the TL
The heavily imported "system/cpus.h" header includes "accel-ops.h"
to get AccelOpsClass type declaration. Reduce headers pressure by
forward declaring it in "qemu/typedefs.h", where we already
declare the AccelCPUState type.
Reduce "system/cpus.h" inclusions by only including
"system/accel-ops.h"
Hi Xiaoyao,
> First, it's not a good practice that values in env->features[] cannot be
> directly used for guest CPUID in void cpu_x86_cpuid(), but require further
> adjustment there. env->features[] are supposed to be finalized at cpu
> realization, so that after it env->features[] is reliable.
>
U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it
is not perfect.
With both builds, executing the VESA ROM causes an intermittent hang, at
least on some AMD CPUs.
With qemu-x86_64 kvm cannot be used since the move to long mode (64-bit)
is done in a way that works on real har
On 3/6/2025 10:52 AM, Denis V. Lunev wrote:
On 3/6/25 16:16, Andrey Drobyshev wrote:
On 3/5/25 11:19 PM, Steven Sistare wrote:
On 3/5/2025 11:50 AM, Andrey Drobyshev wrote:
On 3/4/25 9:05 PM, Steven Sistare wrote:
On 2/28/2025 1:37 PM, Andrey Drobyshev wrote:
On 2/28/25 8:35 PM, Andrey Droby
At the top of linux-user/aarch64/cpu_loop.c we define a set of
macros for reading and writing data and code words, but we never
use these macros. Delete them.
Signed-off-by: Peter Maydell
---
linux-user/aarch64/cpu_loop.c | 48 ---
1 file changed, 48 deletions(-)
On Thu, 6 Mar 2025 at 16:39, Peter Maydell wrote:
>
> The definition of SCR_EL3.RW says that its effective value is 1 if:
> - EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1
> - the effective value of SCR_EL3.{EEL2,NS} is {1,0} (i.e. we are
>Secure and Secure EL2 is disa
On 3/6/25 08:35, Pierrick Bouvier wrote:
On 3/6/25 08:26, Richard Henderson wrote:
On 3/5/25 22:41, Pierrick Bouvier wrote:
Work towards having a single binary, by removing duplicated object files.
hw/hyperv/hyperv.c was excluded at this time, because it depends on target
dependent symbols:
-
From: Denis Rastyogin
Fix possible overflow in 1 << (DF_BITS(df) - 2) when DF_BITS(df)
is 64 by using a 64-bit integer for the shift operation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Reported-by: Dmitriy Fedin
Signed-off-by: Denis Rastyogin
Reviewed-by: Peter Maydel
On 3/6/25 08:26, Richard Henderson wrote:
On 3/5/25 22:41, Pierrick Bouvier wrote:
Work towards having a single binary, by removing duplicated object files.
hw/hyperv/hyperv.c was excluded at this time, because it depends on target
dependent symbols:
- from system/kvm.h
- kvm_check_extens
Am 04.03.2025 um 17:15 hat Daniel P. Berrangé geschrieben:
> On Tue, Mar 04, 2025 at 03:52:31PM +, Alberto Faria wrote:
> > FUA emulation code is already is place.
> >
> > Signed-off-by: Alberto Faria
> > ---
> > hw/scsi/scsi-disk.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the
AST2700 A1 EVB.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 18f7c450da..82f42582fa 100644
--- a/hw/arm/aspe
Move over to use this API before making the code even more complicated.
Signed-off-by: Simon Glass
---
(no changes since v3)
Changes in v3:
- Add new patch to use the new e820 API
arch/x86/cpu/qemu/e820.c | 48 ++--
1 file changed, 12 insertions(+), 36 dele
Add support for an environment stored in the first partition of the
disk, which is assumed to hold a FAT filesystem.
Support the 'cat' command as it is useful for looking at extlinux.conf
files.
Signed-off-by: Simon Glass
---
(no changes since v1)
configs/qemu-x86_64_defconfig | 6 --
con
Provide the 'dhry' command, which helps to check that kvm is being used
properly with QEMU.
Signed-off-by: Simon Glass
---
(no changes since v1)
configs/qemu-x86_64_defconfig | 1 +
configs/qemu-x86_defconfig| 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/qemu-x86_64_defconfi
Directly call cpu_set_pc() instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250122093028.52416-2-phi...@linaro.org>
---
hw/core/generic-loader.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/core/generic-
On 2/28/25 9:24 AM, Duan, Zhenzhong wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Subject: Re: [PATCH rfcv2 05/20] vfio/iommufd: Implement [at|de]tach_hwpt
>> handlers
>>
>>
>>
>>
>> On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>>> Implement [at|de]tach_hwpt handlers in VFIO subsy
This option is supported by both gcc (since 4.7) and clang (since
7.0). Not only does this make the linkers job easier by reducing the
amount of ELF it needs to parse it also reduces the total build size
quite considerably. In my case a default build went from 5.8G to
3.9G (vs 1.9G for --disable-de
Rather than maintaining a mix of system / user code for CPU
class properties, move system properties to cpu-system.c
and user ones to the new cpu-user.c unit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-18-phi...@linaro.org>
---
MAINTAI
We checked the page flags with page_get_flags(), so
locking the page is superfluous. Remove the lock_user()
calls and directly use g2h() in place.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250217130610.18313-5-phi...@lina
This was missed at the time.
Fixes: 812b31d3f91 ("configs: rename default-configs to configs and reorganise")
Signed-off-by: Greg Kurz
---
docs/devel/build-system.rst | 10 +-
docs/devel/kconfig.rst | 16
2 files changed, 13 insertions(+), 13 deletions(-)
diff --gi
On 06/03/2025 18.42, Thomas Huth wrote:
On 05/03/2025 13.25, Philippe Mathieu-Daudé wrote:
Hi Daniel,
On 4/3/25 19:33, Daniel P. Berrangé wrote:
There are two race conditions in the recently added virtio balloon
test
* The /dev/vda device node is not ready
* The virtio-balloon driver has
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
be RAO/WI. We don't enforce this. This isn't a problem yet because
at the moment all of our CPU types with AArch64 support AArch32 at
all exception levels, but in the future this is likely to no longer
be true. Enforce the RAO/WI
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On 2025-03-05 17:06, Daniel P. Berrangé wrote:
On Mon, Feb 24, 2025 at 01:04:47PM +0100, Shalini Chellathurai Saroja
wrote:
Add Control-Program Identification (CPI) to the QEMU Object
Model (QOM). The CPI identifiers provide information about
the guest operating system. The CPI identifiers are:
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Hi Zhao,
On 3/6/25 8:50 AM, Zhao Liu wrote:
> Hi Dongli,
>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index b6d6167910..61a671028a 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -7115,6 +7115,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
>> uint32_t
On 6/3/25 18:41, Greg Kurz wrote:
This was missed at the time.
Fixes: 812b31d3f91 ("configs: rename default-configs to configs and reorganise")
Signed-off-by: Greg Kurz
---
docs/devel/build-system.rst | 10 +-
docs/devel/kconfig.rst | 16
2 files changed, 13 in
On 6/3/25 17:23, Pierrick Bouvier wrote:
On 3/6/25 08:19, Richard Henderson wrote:
On 3/5/25 22:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/syndbg.c | 7 ---
hw/hyperv/meson.build | 2 +-
2 files changed, 5 ins
This patchset intends to decouple existing quirks from legacy mode.
Currently all quirks depends on legacy mode (except x-igd-opregion),
which includes following conditions:
* Machine type is i440fx
* IGD device is at guest BDF 00:02.0
* VBIOS in ROM BAR or file
* VGA IO/MMIO ranges are claimed by
So far, IGD-specific quirks all require enabling legacy mode, which is
toggled by assigning IGD to 00:02.0. However, some quirks, like the BDSM
and GGC register quirks, should be applied to all supported IGD devices.
A new config option, x-igd-legacy-mode=[on|off|auto], is introduced to
control the
Both enable OpRegion option (x-igd-opregion) and legacy mode require
setting up OpRegion copy for IGD devices. As the config quirk no longer
depends on legacy mode, we can now handle x-igd-opregion option there
instead of in vfio_realize.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 14 ++
A new option will soon be introduced to decouple the LPC bridge/Host
bridge ID quirk from legacy mode. To prepare for this, move the LPC
bridge initialization into a separate function.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 122 +-
1 file
The KVMGT/GVT-g vGPU also exposes OpRegion. But unlike IGD passthrough,
it only needs the OpRegion quirk. A previous change moved x-igd-opregion
handling to config quirk breaks KVMGT functionality as it brings extra
checks and applied other quirks. Here we check if the device is mdev
(KVMGT) or not
The actual IO BAR4 write quirk in vfio_probe_igd_bar4_quirk was removed
in previous change, leaving the function not matching its name, so move
it into the newly introduced vfio_config_quirk_setup. There is no
functional change in this commit.
For now, to align with current legacy mode behavior, i
IGD devices require device-specific quirk to be applied to their PCI
config space. Currently, it is put in the BAR4 quirk that does nothing
to BAR4 itself. Add a placeholder for PCI config space quirks to hold
that quirk later.
Signed-off-by: Tomita Moeko
---
hw/vfio/pci-quirks.c | 5 +
hw/v
Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM)
in host address space, direct access to GSM is prohibited, and it is
not mapped to guest address space. Both host and guest accesses GSM
indirectly through the second half of MMIO BAR0 (GTTMMADR).
Guest firmware only need to re
Hi Cédric,
We have a custom machine and a custom image using the AST27x0 A0. I ran
some of our internal tests using these patches. They even fixed some of the
errors we’d been seeing recently!
I’m also working on testing through the A1 patches, will reply to those soon.
Thanks,
Nabih
On Thu, Ma
The definition of SCR_EL3.RW says that its effective value is 1 if:
- EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1
- the effective value of SCR_EL3.{EEL2,NS} is {1,0} (i.e. we are
Secure and Secure EL2 is disabled)
We implement the second of these in arm_el_is_aa64(),
We already call env_archcpu() multiple times within the
exception_return helper function, and we're about to want to
add another use of the ARMCPU pointer. Add a local variable
cpu so we can call env_archcpu() just once.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-a64.c | 7 ---
1
TCGCPUOps structure makes more sense in the accelerator context
rather than hardware emulation. Move it under the accel/tcg/ scope.
Mechanical change doing:
$ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \
$(git grep -l hw/core/tcg-cpu-ops.h)
Signed-off-by: Philippe Mathieu-Dau
The arm_cpu_data_is_big_endian() and related functions are now used
only in target/arm; they can be moved to internals.h.
The motivation here is that we would like to move arm_current_el()
to internals.h.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 48 -
On 3/5/25 22:41, Pierrick Bouvier wrote:
Replace TARGET_PAGE.* by runtime calls
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/syndbg.c| 7 ---
hw/hyperv/meson.build | 2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/hyperv/syndbg.c b/hw/hyperv/syndbg.c
index d
Hi Zhenzhong,
On 2/28/25 9:16 AM, Duan, Zhenzhong wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Subject: Re: [PATCH rfcv2 03/20] HostIOMMUDevice: Introduce realize_late
>> callback
>>
>>
>>
>>
>> On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>>> Currently we have realize() callback
201 - 300 of 304 matches
Mail list logo
