On 3/6/25 08:39, Peter Maydell wrote:
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
be RAO/WI. We don't enforce this. This isn't a problem yet because
at the moment all of our CPU types with AArch64 support AArch32 at
all exception levels, but in the future this is likely to no longer
be true. Enforce the RAO/WI behaviour.
Note that we handle "reset value should honour RES1 bits" in the same
way that SCR_EL3 does, via a reset function.
Signed-off-by: Peter Maydell<peter.mayd...@linaro.org>
---
target/arm/helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
