On 2/28/25 21:25, Brian Cain wrote:
From: Brian Cain <bc...@quicinc.com>

Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
---
  target/hexagon/cpu_bits.h       |  2 ++
  target/hexagon/gen_tcg_funcs.py | 32 +++++++++++++++++++-------------
  2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index ff596e2a94..6582bb4f16 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -37,6 +37,8 @@ enum hex_cause {
      HEX_CAUSE_PC_NOT_ALIGNED =  0x01e,
      HEX_CAUSE_PRIV_NO_UREAD  =  0x024,
      HEX_CAUSE_PRIV_NO_UWRITE =  0x025,
+    HEX_CAUSE_PRIV_USER_NO_GINSN = 0x01a,
+    HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b,
  };
#define PACKET_WORDS_MAX 4
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index c2ba91ddc0..65bfa046b8 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -21,7 +21,7 @@
  import re
  import string
  import hex_common
-
+from textwrap import dedent
##
  ## Generate the TCG code to call the helper
@@ -50,6 +50,18 @@ def gen_tcg_func(f, tag, regs, imms):
f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n") + if "A_PRIV" in hex_common.attribdict[tag]:
+        f.write(dedent("""\
+#ifdef CONFIG_USER_ONLY
+    hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_SINSN);
+#else
+"""))
+    if "A_GUEST" in hex_common.attribdict[tag]:
+        f.write(dedent("""\
+#ifdef CONFIG_USER_ONLY
+    hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_GINSN);
+#else
+"""))


You add new exceptions, but do not handle them in cpu_loop.

I suppose this is not actually a regression, because we already
fail to handle illegal instruction exceptions in cpu_loop.

But you'll want to fix both.  :-)


r~

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