On 3/6/25 08:39, Peter Maydell wrote:
+/* Return the effective value of SCR_EL3.RW */
+static inline bool arm_scr_rw_eff(CPUARMState *env)
+{
+    /*
+     * SCR_EL3.RW has an effective value of 1 if:
+     *  - we are NS and EL2 is implemented but doesn't support AArch32
+     *  - we are S and EL2 is enabled (in which case it must be AArch64)
+     */
+    ARMCPU *cpu = env_archcpu(env);
+    bool ns_and_no_aarch32_el2 = arm_feature(env, ARM_FEATURE_EL2) &&
+        (env->cp15.scr_el3 & SCR_NS) &&
+        !cpu_isar_feature(aa64_aa32_el1, cpu);
+    bool s_and_el2_enabled =
+        (env->cp15.scr_el3 & (SCR_NS | SCR_EEL2)) == SCR_EEL2;
+
+    return ns_and_no_aarch32_el2 || s_and_el2_enabled ||
+        (env->cp15.scr_el3 & SCR_RW);
+}

The computation here can be simplified.

    if (env->cp15.scr_el3 & SCR_RW) {
        return true;
    }
    if (env->cp15.scr_el3 & SCR_NS) {
        return arm_feature(env, ARM_FEATURE_EL2) &&
               !cpu_isar_feature(aa64_aa32_el1, cpu);
    } else {
        return env->cp15.scr_el3 & SCR_EEL2;
    }

Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~

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