CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7
("Use a dedicated function to request exit from execution
loop"), tlb_flush() and tb_flush() are related to TCG
accelerator.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250123234415.59850-17-phi...@linaro.org>
---
cpu-target.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index b925b9391e8..48446c90212 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -46,22 +46,25 @@
#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
{
- CPUState *cpu = opaque;
+ if (tcg_enabled()) {
+ CPUState *cpu = opaque;
- /*
- * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
- * version_id is increased.
- */
- cpu->interrupt_request &= ~0x01;
- tlb_flush(cpu);
+ /*
+ * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
+ * version_id is increased.
+ */
+ cpu->interrupt_request &= ~0x01;
- /*
- * loadvm has just updated the content of RAM, bypassing the
- * usual mechanisms that ensure we flush TBs for writes to
- * memory we've translated code from. So we must flush all TBs,
- * which will now be stale.
- */
- tb_flush(cpu);
+ tlb_flush(cpu);
+
+ /*
+ * loadvm has just updated the content of RAM, bypassing the
+ * usual mechanisms that ensure we flush TBs for writes to
+ * memory we've translated code from. So we must flush all TBs,
+ * which will now be stale.
+ */
+ tb_flush(cpu);
+ }
return 0;
}
--
2.47.1
