On 2/26/25 17:26, Cédric Le Goater wrote:
On 2/26/25 15:12, BALATON Zoltan wrote:
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
VFIO PCI never worked on PPC32 nor ARM, S390x is 64-bit, it might have
worked on i386 long ago but we have no plans to further support VFIO
on any 32-bit host platforms
On Mon, 3 Mar 2025, Philippe Mathieu-Daudé wrote:
On 26/2/25 18:57, BALATON Zoltan wrote:
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
On 2/26/25 15:12, BALATON Zoltan wrote:
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
VFIO PCI never worked on PPC32 nor ARM, S390x is 64-bit, it might have
wo
On Mon, Mar 03, 2025 at 05:13:56PM +0530, Prasad Pandit wrote:
> Hello Peter,
>
> On Fri, 28 Feb 2025 at 19:13, Peter Xu wrote:
> > We should be able to do multifd's flush and sync before VM
> > stopped in postcopy_start()..
> >
> > What I actually think the easiest is to do flush and sync once i
On 3/3/25 15:28, Zhao Liu wrote:
-pub fn init_full<'timer, 'opaque: 'timer, T, F>(
-&'timer mut self,
+pub fn new_full<'opaque, T, F>(
timer_list_group: Option<&TimerListGroup>,
clk_type: ClockType,
scale: u32,
attributes: u32,
_cb
On Thu, Feb 27, 2025 at 03:22:15PM +0100, Paolo Bonzini wrote:
> Date: Thu, 27 Feb 2025 15:22:15 +0100
> From: Paolo Bonzini
> Subject: [PATCH 08/12] rust: hpet: do not access fields of SysBusDevice
> X-Mailer: git-send-email 2.48.1
>
> Fields of SysBusDevice must only be accessed with the BQL ta
On 3/3/25 15:43, Paolo Bonzini wrote:
On 2/26/25 17:26, Cédric Le Goater wrote:
On 2/26/25 15:12, BALATON Zoltan wrote:
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
VFIO PCI never worked on PPC32 nor ARM, S390x is 64-bit, it might have
worked on i386 long ago but we have no plans to further su
On 3/3/25 15:46, Paolo Bonzini wrote:
On 3/3/25 15:30, Philippe Mathieu-Daudé wrote:
I see PPC is defined in target/ppc/Kconfig so I think these mark the target not the host. Vfio-pci works with qemu-system-ppc
I've seen people do this on x86_64 host
Since this patch does:
LINUX && PCI &
On Thu, Feb 27, 2025 at 03:22:17PM +0100, Paolo Bonzini wrote:
> Date: Thu, 27 Feb 2025 15:22:17 +0100
> From: Paolo Bonzini
> Subject: [PATCH 10/12] rust: memory: wrap MemoryRegion with Opaque<>
> X-Mailer: git-send-email 2.48.1
>
> Signed-off-by: Paolo Bonzini
> ---
> rust/qemu-api/src/bindin
On Mon, Mar 3, 2025 at 3:31 AM Alistair Francis wrote:
>
> We previously allocate the fifo on reset and never free it, which means
> we are leaking memory.
>
> Instead let's allocate on realize and free on unrealize.
>
> Signed-off-by: Alistair Francis
> ---
> hw/char/sifive_uart.c | 44
On Thu, Feb 27, 2025 at 03:22:12PM +0100, Paolo Bonzini wrote:
> Date: Thu, 27 Feb 2025 15:22:12 +0100
> From: Paolo Bonzini
> Subject: [PATCH 05/12] rust: irq: wrap IRQState with Opaque<>
> X-Mailer: git-send-email 2.48.1
>
> Signed-off-by: Paolo Bonzini
> ---
> rust/qemu-api/src/irq.rs| 1
On 3/3/25 15:43, Paolo Bonzini wrote:
On 2/26/25 17:26, Cédric Le Goater wrote:
On 2/26/25 15:12, BALATON Zoltan wrote:
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
VFIO PCI never worked on PPC32 nor ARM, S390x is 64-bit, it might have
worked on i386 long ago but we have no plans to further su
On 3/3/25 16:26, BALATON Zoltan wrote:
On Mon, 3 Mar 2025, Cédric Le Goater wrote:
On 3/3/25 15:46, Paolo Bonzini wrote:
On 3/3/25 15:30, Philippe Mathieu-Daudé wrote:
I see PPC is defined in target/ppc/Kconfig so I think these mark the target not the host. Vfio-pci works with qemu-system-ppc
On Mon, Mar 03, 2025 at 03:51:25PM +0100, Paolo Bonzini wrote:
> Date: Mon, 3 Mar 2025 15:51:25 +0100
> From: Paolo Bonzini
> Subject: Re: [PATCH 04/12] rust: timer: wrap QEMUTimer with Opaque<> and
> express pinning requirements
>
> On 3/3/25 15:28, Zhao Liu wrote:
> > > -pub fn init_full<'
On 2/28/2025 11:28 PM, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/sys_macros.h | 8 +--
target/hexagon/op_helper.c | 104
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/sys_macro
On Mon, Mar 03, 2025 at 02:35:10PM +0100, Raman Dzehtsiar wrote:
> This patch extends the blockdev-backup QMP command to allow users to specify
> how to behave when IO errors occur during copy-before-write operations.
> Previously, the behavior was fixed and could not be controlled by the user.
>
On Sat, Mar 1, 2025 at 2:14 AM Markus Armbruster wrote:
> Paolo Bonzini writes:
>
> > On 2/28/25 22:20, Patrick Venture wrote:
> >> From: Peter Foley
> >> e.g.
> >> qemu: Uninitialized value was created by an allocation of
> 'key_in_cur.i' in the stack frame
> >> qemu: #0 0xc49f489c in keyv
And interestingly enough, it appears that execution continues even with
early return from get_page_addr_code_hostp:
https://gitlab.com/qemu-project/qemu/-/blob/master/accel/tcg/translate-all.c?ref_type=heads#L308
Which implies that we could still have an uninitialized value here:
https://gitlab.co
For reference, the full output from msan looks like:
==4872==WARNING: MemorySanitizer: use-of-uninitialized-value
#0 0xc681ef98 in tb_gen_code
third_party/qemu/accel/tcg/translate-all.c:358:21
#1 0xc67f2520 in cpu_exec_loop
third_party/qemu/accel/tcg/cpu-exec.c:993:22
#2 0x
On Thu, Feb 27, 2025 at 03:22:16PM +0100, Paolo Bonzini wrote:
> Date: Thu, 27 Feb 2025 15:22:16 +0100
> From: Paolo Bonzini
> Subject: [PATCH 09/12] rust: sysbus: wrap SysBusDevice with Opaque<>
> X-Mailer: git-send-email 2.48.1
>
> Signed-off-by: Paolo Bonzini
> ---
> rust/qemu-api/src/bindin
On 3/3/25 15:30, Philippe Mathieu-Daudé wrote:
I see PPC is defined in target/ppc/Kconfig so I think these mark the
target not the host. Vfio-pci works with qemu-system-ppc
I've seen people do this on x86_64 host
Since this patch does:
LINUX && PCI && (... X86_64 ...)
these users won't
On 3/3/25 11:28, Akihiko Odaki wrote:
usb-storage automatically adds a SCSI device, but it limits
configurability of the added SCSI device and causes usability
problems as observed in:
https://gitlab.com/libvirt/libvirt/-/issues/368
Allow manually adding SCSI device when the drive option is not
Hi Nicolin,
> -Original Message-
> From: Nicolin Chen
> Sent: Thursday, February 6, 2025 6:58 PM
> To: Shameerali Kolothum Thodi
> Cc: Eric Auger ; ddut...@redhat.com; Peter
> Maydell ; Jason Gunthorpe ;
> Daniel P. Berrangé ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; Linuxarm ; Wang
On Mon, 3 Mar 2025, Cédric Le Goater wrote:
On 3/3/25 15:46, Paolo Bonzini wrote:
On 3/3/25 15:30, Philippe Mathieu-Daudé wrote:
I see PPC is defined in target/ppc/Kconfig so I think these mark the
target not the host. Vfio-pci works with qemu-system-ppc
I've seen people do this on x86_64 ho
> On Mar 3, 2025, at 6:19 AM, John Levon wrote:
>
> On Fri, Feb 28, 2025 at 05:09:00PM +, Jag Raman wrote:
>
>> I appreciate you posting the patches. I didn't author the patches, actually;
>> John Johnson did it.
>
> I'll adjust the Author field and fix up the "Originally-by" tags for the
On 3/3/25 14:48, Zhao Liu wrote:
@@ -156,7 +157,7 @@ pub struct HPETTimer {
/// timer N index within the timer block (`HPETState`)
#[doc(alias = "tn")]
index: usize,
-qemu_timer: Option>,
+qemu_timer: Option>>,
I'm removing this Option<> wrapper in migration series. Th
On 3/3/25 16:48, Cédric Le Goater wrote:
On 3/3/25 16:26, BALATON Zoltan wrote:
On Mon, 3 Mar 2025, Cédric Le Goater wrote:
On 3/3/25 15:46, Paolo Bonzini wrote:
On 3/3/25 15:30, Philippe Mathieu-Daudé wrote:
I see PPC is defined in target/ppc/Kconfig so I think these mark the target not the h
Hi,
On 27/12/24 21:24, Philippe Mathieu-Daudé wrote:
ARM_GICV3 is not restricted to TCG and can be used on HVF.
Philippe Mathieu-Daudé (2):
hw/intc: Remove TCG dependency on ARM_GICV3
First reviewed/tested patch queued via hw-misc tree.
Thanks,
Phil.
On 3/3/25 10:54, Jamin Lin wrote:
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Modified the hwmon path to use a wildcard to handle different SDK versions:
May be add a little comment about the new ast2700-a0-default OpenBMC
build in v09.05.
On 3/3/25 10:54, Jamin Lin wrote:
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/functional/test_aarch64_aspeed.py | 12 ++--
1 file changed, 6 insertions(+), 6
On Mon, Mar 03, 2025 at 03:53:29PM +0100, Philippe Mathieu-Daudé wrote:
> On 3/3/25 15:43, Paolo Bonzini wrote:
> > On 2/26/25 17:26, Cédric Le Goater wrote:
> > > On 2/26/25 15:12, BALATON Zoltan wrote:
> > > > On Wed, 26 Feb 2025, Cédric Le Goater wrote:
> > > > > VFIO PCI never worked on PPC32 n
On 3/3/25 10:54, Jamin Lin wrote:
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/functional/test_aarch64_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_asp
Il lun 3 mar 2025, 16:05 Cédric Le Goater ha scritto:
> On 3/3/25 15:46, Paolo Bonzini wrote:
> > On 3/3/25 15:30, Philippe Mathieu-Daudé wrote:
> > I see PPC is defined in target/ppc/Kconfig so I think these mark the
> target not the host. Vfio-pci works with qemu-system-ppc
> >>>
> >>> I've
On Mon, 3 Mar 2025 at 15:49, Cédric Le Goater wrote:
> Why are we keeping qemu-system-ppc and qemu-system-i386, and arm,
> since qemu-system-ppc64 and qemu-system-x86_64 should be able to
> run the same machines ?
They're not identical -- for example "-cpu max" on
qemu-system-arm is a 32-bit CPU
On Mon, Mar 03, 2025 at 03:21:57PM +, Shameerali Kolothum Thodi wrote:
> I am working on the above now and have quick question to you😊.
>
> Looking at the smmu_dev_attach_viommu() fn here[0],
> it appears to do the following:
>
> 1. Alloc a s2_hwpt if not allocated already and attach it.
> 2.
Xianglai,
There is a similar modification already, just wait a moment :)
https://lists.nongnu.org/archive/html/qemu-devel/2025-02/msg01537.html
Regards
Bibo Mao
On 2025/3/3 下午2:30, Xianglai Li wrote:
The commit 5a99a10da6cf ("target/loongarch: fix vcpu reset command word issue")
fixes the er
On 3/3/25 03:31, Alistair Francis wrote:
We previously allocate the fifo on reset and never free it, which means
we are leaking memory.
Instead let's allocate on realize and free on unrealize.
Signed-off-by: Alistair Francis
---
hw/char/sifive_uart.c | 44 +++-
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" f
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
To follow the machine deprecation rule, the initial machine "ast2700-evb" is
aliased to "ast2700a0-evb." In the future, we will alias "ast2700-evb" to new
SoCs, such as "ast2700a1-evb."
Signed-o
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin
---
docs/specs/aspeed-intc.rst | 136 +
docs/specs/index.rst | 1 +
2 files changed, 137 insertions(+)
create mode 100644 docs/specs/aspeed-intc.rst
diff --git a/docs/sp
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Modified the hwmon path to use a wildcard to handle different SDK versions:
"cat /sys/bus/i2c/devices/1-004d/hw
Power CPUs place RAM memory regions for each chip (NUMA node) at
fixed locations in the real address space, resulting in a sparse
(disjoint) RAM address layout.
Use the new NUMA machine class attribute numa_skip_ram_container to
allow pnv machine init to lay out NUMA node memory regions into the
s
IBM Power machines put NUMA node RAM at fixed addresses per node,
rather than packing it densely from address 0. This series implements
support for this by allowing machines to override the core NUMA
memory container packing, and add their own RAM regions to the
system memory space.
Thanks,
Nick
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds o
Enable NUMA topology configuration for the powernv machine by
filling the necessary attributes and methods.
pnv_possible_cpu_arch_ids() runs before pnv_init(), so the hacky
big-core topology adjustment has to be moved there.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 101
NUMA machines with sparse address topologies do not want all NUMA
regions packed densely inside the MachineState.ram container region.
Add a machine class attribute that skips creating this container
region. Individual NUMA memory device regions are recorded in NodeInfo
where the machine init can a
Currently the built plugins can only be found in the build directory.
This patch lists them as installable objects, which will be copied
into qemu_moddir with `make install`.
Signed-off-by: Christoph Müllner
---
contrib/plugins/meson.build | 8 ++--
1 file changed, 6 insertions(+), 2 deletio
Linux power management code accesses these registers for pstate
management. Wire up a very simple implementation.
Signed-off-by: Nicholas Piggin
---
After OCC fixes in QEMU pnv model and skiboot (since they have suffered
some bitrot), Linux will start performing PM SPR accesses. This is a
very si
On 18/2/25 16:54, BALATON Zoltan wrote:
Add description and set category for eTSEC device so it shows up
better in -device help.
Signed-off-by: BALATON Zoltan
---
hw/net/fsl_etsec/etsec.c | 2 ++
1 file changed, 2 insertions(+)
Patch queued, thanks!
On 18/2/25 17:26, Philippe Mathieu-Daudé wrote:
accel/Kconfig: Link XenPVH with GPEX PCIe bridge
hw/arm: Do not expose the virt machine on Xen-only binary
hw/arm/xen-pvh: Do not allow specifying any CPU type
hw/xen/xen-pvh: Reduce included headers
hw/xen/xen-hvm: Reduce included h
On Mon, 3 Mar 2025, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 10/2/25 17:03, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this and not initialise these registers befo
Hi Patrick,
On 27/2/25 16:42, Patrick Venture wrote:
eth_hdr requires 2 byte alignment
Signed-off-by: Patrick Venture
---
hw/net/ftgmac100.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
@@ -1028,6 +1032,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc,
On 1/3/25 15:35, BALATON Zoltan wrote:
No need to open code it so use the simple object type declaration.
Signed-off-by: BALATON Zoltan
---
hw/nvram/eeprom_at24c.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 1/3/25 15:35, BALATON Zoltan wrote:
Calling memset to zero memory is not needed after g_malloc0 which
already clears memory. These used to be in separate functions but
after some patches the memset ended up after g_malloc0 and thus can be
dropped.
Fixes: 4f2c6448c3 (hw/nvram/eeprom_at24c: Mak
On Fri, Feb 28, 2025 at 05:09:00PM +, Jag Raman wrote:
> I appreciate you posting the patches. I didn't author the patches, actually;
> John Johnson did it.
I'll adjust the Author field and fix up the "Originally-by" tags for the next
round, thanks.
> You could use your name as the author si
The HRMOR and LPCR registers are involved with MMU translations that
are not tagged in the TLB (i.e., with mmuidx), so the TLB needs to be
flushed when these are changed, e.g., as PIDR, LPIDR already do.
target/ppc: add missing TLB flushes for MMU SPR updates
Signed-off-by: Nicholas Piggin
---
t
The IAMR and AMR registers are involved with MMU translations that
are not tagged in the TLB (i.e., with mmuidx), so the TLB needs to be
flushed when these are changed, e.g., as PIDR, LPIDR already do.
This moves AMR and IAMR write to helpers rather than use tlb_need_flush
because they can be writ
Avoid TLB flushing and hflags recomputation if LPCR, LPIDR, or PIDR
are written with the same value. This is observed to happen in some
cases (e.g., in hypervisor real-mode exit fastpath handlers).
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.c | 8 +++-
target/ppc/misc_helper.
On 1/3/25 15:35, BALATON Zoltan wrote:
The init_rom can write values to the beginning of the memory but these
are overwritten by values from a backing file that covers the whole
memory. Do the init_rom handling only if it would not be overwritten.
Signed-off-by: BALATON Zoltan
---
hw/nvram/ee
On 1/3/25 15:35, BALATON Zoltan wrote:
In the realize method error_setg can be used like other places there
already do. The other usage can be replaced with error_report which is
the preferred way instead of directly printing to stderr.
Signed-off-by: BALATON Zoltan
---
hw/nvram/eeprom_at24c.
On 27.02.25 14:44, Roy Hopkins wrote:
Adds an IGVM loader to QEMU which processes a given IGVM file and
applies the directives within the file to the current guest
configuration.
The IGVM loader can be used to configure both confidential and
non-confidential guests. For confidential guests, the
On Fri, Feb 28, 2025 at 09:57:08PM +0200, Nir Soffer wrote:
> This test depends on TarFile.addfile() to add tar member header without
> writing the member data, which we write ourself using qemu-nbd. Python
> 3.13 changed the function in a backward incompatible way[1] to require a
> file object for
On Mon, 10 Feb 2025, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this and not initialise these registers before expecting
interrupts. Use existing vendor property for Fr
Am 1. März 2025 16:02:05 UTC schrieb BALATON Zoltan :
>On Mon, 10 Feb 2025, BALATON Zoltan wrote:
>> The interrupt enable registers are not reset to 0 on Freescale eSDHC
>> but some bits are enabled on reset. At least some U-Boot versions seem
>> to expect this and not initialise these registers
On Mon, Mar 3, 2025 at 8:35 AM Stefan Hajnoczi wrote:
> GitLab says:
> "There has been a timeout failure or the job got stuck. Check your
> timeout limits or try again"
>
> Duration: 77 minutes 13 seconds
> Timeout: 1h (from project)
>
> It ran 17 minutes longer than the job timeout.
The job only
On Mon, Mar 3, 2025 at 11:24 AM 汪鹏程 wrote:
>
> What about plugins under `tests/tcg/plugins/`?
It feels a bit odd to install something from the tests directory.
If certain plugins in tests/tcg/plugins are of general use (not just
for testing) then it might be
reasonable to move them to contrib/plu
Perform !guest_visible memory accesses without modifying R/C bits.
It's arguable whether !guest_visible memory accesses should modify
R/C bits. i386 seems to set accessed/dirty bit updates for "probe"
accesses, but ppc with radix MMU does not. Follow the ppc/radix
lead and perform the accesses wit
The LPC model has only supported serirqs (ISA device IRQs), however
there are internal sources that can raise other interrupts. Update the
device to handle these interrupt sources.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_lpc.c | 64 +++-
1 file c
Hi Richard,
On 17/2/25 00:08, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-has.h| 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h
Hello,
On Sun, 2 Mar 2025, Hab Gallagher wrote:
I have interest in contributing patches to extend qemu's powerpc graphics
card emulation to include more comprehensive support for gamma. Some
classic mac applications will balk at launch if the graphics card doesn't
claim enough support for gamma
On Mon, 3 Mar 2025, Nicholas Piggin wrote:
Perform !guest_visible memory accesses without modifying R/C bits.
It's arguable whether !guest_visible memory accesses should modify
R/C bits. i386 seems to set accessed/dirty bit updates for "probe"
accesses, but ppc with radix MMU does not. Follow th
Hi Zoltan,
On 10/2/25 17:03, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this and not initialise these registers before expecting
interrupts. Use existing vendor proper
On Fri, Feb 28, 2025 at 10:34:34PM +0530, Ani Sinha wrote:
> Currently call to x86_firmware_configure() -> pc_system_parse_ovmf_flash()
> happens only when SEV is enabled. Fortunately, X86_FW_OVMF is turned on
> automatically when SEV is enabled and therefore, we never end up calling
> pc_system_p
On 3/2/25 11:31 PM, Alistair Francis wrote:
We previously allocate the fifo on reset and never free it, which means
we are leaking memory.
Instead let's allocate on realize and free on unrealize.
Signed-off-by: Alistair Francis
---
Reviewed-by: Daniel Henrique Barboza
hw/char/sifive_
Support setting textra32.sselect or textra64.sselect to 1 (scontext).
The trigger will only match if the content of scontext matches the value
in svalue, after it is masked as configured in sbytemask.
Signed-off-by: Florian Lugou
---
target/riscv/debug.c | 75 +++-
scontext size is 16 bits on RV32 and 32 bits on RV64, as recommended by
version 1.0 2025-02-21 of the debug specification.
When the Smstateen extension is implemented, accessibility to the
scontext CSR is controlled by bit 57 of the [mh]stateen0 CSRs.
Signed-off-by: Florian Lugou
---
target/ris
Hello,
v2: Rebasing the patch series on top of the maintainer's tree.
Thank you,
Florian Lugou (2):
target/riscv: Add scontext CSR handling
target/riscv: Support matching scontext in Sdtrig's textra CSRs
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 5 +++
target/riscv/csr.c
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Signed-off-by: Jam
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly def
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jam
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/h
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_as
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
---
hw/arm/as
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 07b0c7c1fd..8df6a97a28 100755
--- a/tests/functional/test_
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 8df6a97a28..c25c966278 100755
--- a/tests/functional/test_aarch64_aspeed.py
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Introduce "asp
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/intc/asp
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/misc/aspeed_scu.h | 2 ++
hw/misc/aspeed_scu.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/i
On 17/2/25 00:08, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 3 +--
tcg/optimize.c | 19 +++
tcg/tcg-op.c | 10 +-
tcg/tcg.c | 13 -
docs/devel/tcg-ops.rst | 2 +-
5 files chan
On 17/2/25 00:07, Richard Henderson wrote:
In 7536b82d288 we lost the rI constraint that allowed the use of
RSB to perform reg = imm - reg. At the same time, drop support
for reg = reg - imm, which is now transformed generically to
addition, and need not be handled by the backend.
Signed-off-by
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a reg
usb-storage automatically adds a SCSI device, but it limits
configurability of the added SCSI device and causes usability
problems as observed in:
https://gitlab.com/libvirt/libvirt/-/issues/368
Allow manually adding SCSI device when the drive option is not
specified.
Signed-off-by: Akihiko Odaki
On 17/2/25 00:08, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-has.h| 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h| 2 --
On Mon, 3 Mar 2025, Bernhard Beschow wrote:
Am 1. März 2025 16:02:05 UTC schrieb BALATON Zoltan :
On Mon, 10 Feb 2025, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this
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