v1: 1. Refactor INTC model to support both INTC0 and INTC1. 2. Support AST2700 A1. 3. Create ast2700a0-evb machine. v2: To streamline the review process, split the following patch series into three parts. https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_...@aspeedtech.com/ This patch series focuses on cleaning up the INTC model to facilitate future support for the INTC_IO model.
v3: 1. Update and add functional test for AST2700 2. Add AST2700 INTC design guidance and its block diagram. 3. Retaining the INTC naming and introducing a new INTCIO model to support the AST2700 A1. 4. Create ast2700a1-evb machine and rename ast2700a0-evb machine 5. Fix silicon revision issue and support AST2700 A1. v4: 1. rework functional test for AST2700 2. the initial machine "ast2700-evb" is aliased to "ast2700a0-evb. 3. intc: Reduce regs array size by adding a register sub-region 4. intc: split patch for Support setting different register sizes 5. update ast2700a1-evb machine parent to TYPE_ASPEED_MACHINE With the patch applied, QEMU now supports two machines for running AST2700 SoCs: ast2700a0-evb: Designed for AST2700 A0 ast2700a1-evb: Designed for AST2700 A1 Test information 1. QEMU version: https://github.com/qemu/qemu/commit/50d38b8921837827ea397d4b20c8bc5efe186e53 2. ASPEED SDK v09.05 pre-built image https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.05 ast2700-default-obmc.tar.gz (AST2700 A1) https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-default-obmc.tar.gz ast2700-a0-default-obmc.tar.gz (AST2700 A0) https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-a0-default-obmc.tar.gz This patch series depends on the following patch series: https://patchwork.kernel.org/project/qemu-devel/cover/20250303073547.1145080-1-jamin_...@aspeedtech.com/ https://patchwork.kernel.org/project/qemu-devel/cover/20250225075622.305515-1-jamin_...@aspeedtech.com/ Jamin Lin (23): hw/intc/aspeed: Support setting different memory size hw/intc/aspeed: Support setting different register sizes hw/intc/aspeed: Reduce regs array size by adding a register sub-region hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add object type name to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Rename num_ints to num_inpins for clarity hw/intc/aspeed: Add support for multiple output pins in INTC hw/intc/aspeed: Refactor INTC to support separate input and output pin indices hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication hw/intc/aspeed: Add Support for Multi-Output IRQ Handling hw/intc/aspeed: Add Support for AST2700 INTCIO Controller hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 tests/functional/aspeed: Introduce start_ast2700_test API and update hwmon path tests/functional/aspeed: Update test ASPEED SDK v09.05 tests/functional/aspeed: Add test case for AST2700 A1 docs/specs: Add aspeed-intc docs/specs/aspeed-intc.rst | 136 +++++ docs/specs/index.rst | 1 + include/hw/arm/aspeed_soc.h | 3 +- include/hw/intc/aspeed_intc.h | 35 +- include/hw/misc/aspeed_scu.h | 2 + hw/arm/aspeed.c | 33 +- hw/arm/aspeed_ast27x0.c | 276 +++++++--- hw/intc/aspeed_intc.c | 636 ++++++++++++++++++------ hw/misc/aspeed_scu.c | 2 + hw/intc/trace-events | 25 +- tests/functional/test_aarch64_aspeed.py | 47 +- 11 files changed, 942 insertions(+), 254 deletions(-) create mode 100644 docs/specs/aspeed-intc.rst -- 2.34.1
