On Mon, Feb 24, 2025 at 10:33 PM Daniel Henrique Barboza
wrote:
>
> Remove the !kvm_enabled() check in kvm_riscv_reset_vcpu() since the
> function is already being gated by kvm_enabled() in
> riscv_cpu_reset_hold().
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed
On Mon, Feb 24, 2025 at 10:32 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this version I rolled back on the riscv_cpu_reset_hold() changes made
> in patch 1. Peter made an argument about keeping the design the same
> across architectures and I agreed. Patches 2 and 3 are already taking
> care
On 02/03/2025 16:59, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
On 2.03.2025 15:54, Maciej S. Szmigiero wrote:
On 2.03.2025 15:53, Avihai Horon wrote:
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or atta
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie. we check tlb_ps
when get the tlb_ps from tlb->misc or CSR bits.
1. cpu reset
set CSR_PWCL.PTBASE and CSR_STL
some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0,just check the tlb_ps skip
the function and write a log.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 8
1 file changed, 8 insertions(+)
diff --
Some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0,just check the tlb_e skip
the function and check_tlb_ps write a log.
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fucti
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Add VFIOStateBuffer(s) types and the associated methods.
These store received device state buffers and config state waiting to get
loaded into the device.
S
Signed-off-by: Brian Cain
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/cpu.c| 10 +++---
target/hexagon/cpu_helper.c | 17 ++---
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 80f5e23794..4
On 19/02/2025 22:33, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
A new function multifd_queue_device_state() is provided for device to queue
its state for transmission via a multifd channel.
Reviewed-by: Peter Xu
Signed-o
Hi Maciej,
Sorry for the long delay, I have been busy with other tasks.
I got some small comments for the series.
On 19/02/2025 22:33, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Add a basic support for receiving device sta
The link to riscv iommu specification document is incorrect. This patch
updates the said link to point to correct location.
Cc: qemu-ri...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808
Signed-off-by: hemanshu.khilari.foss
---
docs/specs/riscv-iommu.rst | 4 ++--
1 file
QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
and kvm_put_msrs() to restore them to KVM. However, there is no support for
AMD PMU registers. Currently, has_pmu_version and num_pmu_gp_counters are
initialized based on cpuid(0xa), which does not apply to AMD processors.
F
Since perfmon-v2, the AMD PMU supports additional registers. This update
includes get/put functionality for these extra registers.
Similar to the implementation in KVM:
- MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both
use env->msr_global_status.
- MSR_CORE_PERF_GLOBAL_CTRL
Would you mind suggesting how we can move forward with this patchset as:
(1) One patch for kvm_arch_pre_create_vcpu() is picked from Xiaoyao's
patchset.
(2) Dapeng is working on mediated passthrough vPMU QEMU patches. This
patchset doesn't support mediated passthrough vPMU.
This patchset addresse
The initialization of 'has_architectural_pmu_version',
'num_architectural_pmu_gp_counters', and
'num_architectural_pmu_fixed_counters' is unrelated to the process of
building the CPUID.
Extract them out of kvm_x86_build_cpuid().
No functional change.
Signed-off-by: Dongli Zhang
---
Changed sinc
Currently, AMD PMU support isn't determined based on CPUID, that is, the
"-pmu" option does not fully disable KVM AMD PMU virtualization.
To minimize AMD PMU features, remove PERFCORE when "-pmu" is configured.
To completely disable AMD PMU virtualization will be implemented via
KVM_CAP_PMU_CAPAB
On Sun, 2 Mar 2025, Bernhard Beschow wrote:
Am 1. März 2025 16:10:35 UTC schrieb BALATON Zoltan :
On Wed, 15 Jan 2025, BALATON Zoltan wrote:
This allows guests to set the CCSR base address. Also store and return
values of the local access window registers but their functionality
isn't implement
On Sun, Mar 2, 2025 at 11:07 PM hemanshu.khilari.foss
wrote:
>
> The link to riscv iommu specification document is incorrect. This patch
> updates the said link to point to correct location.
>
> Cc: qemu-ri...@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808
> Signed-off-b
On Sun, Mar 2, 2025 at 11:07 PM hemanshu.khilari.foss
wrote:
>
> The link to riscv iommu specification document is incorrect. This patch
> updates the said link to point to correct location.
>
> Cc: qemu-ri...@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808
> Signed-off-b
On Mon, Mar 3, 2025 at 10:46 AM Alistair Francis wrote:
>
> On Sun, Mar 2, 2025 at 11:07 PM hemanshu.khilari.foss
> wrote:
> >
> > The link to riscv iommu specification document is incorrect. This patch
> > updates the said link to point to correct location.
> >
> > Cc: qemu-ri...@nongnu.org
> >
On Mon, Feb 24, 2025 at 10:32 PM Daniel Henrique Barboza
wrote:
>
> We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but
> in no particular order and missing some of them (like env->mstatus).
>
> Create a helper to do that, unclogging reset_vcpu(), and initialize
> env->mstatus
On Mon, Feb 24, 2025 at 10:32 PM Daniel Henrique Barboza
wrote:
>
> We're missing scounteren and senvcfg CSRs, both already present in the
> KVM UAPI.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/kvm/kvm-cpu.
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
This property allows configuring at runtime whether to transfer the
IIUC, in this patch it's not configurable at runtime, so let's drop "at
runtime".
pa
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Allow capping the maximum count of in-flight VFIO device state buffers
queued at the destination, otherwise a malicious QEMU source could
theoretically cause
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different multifd channels can arrive out-of-order.
Therefore, each VFI
On 26/02/2025 15:49, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Since it's important to finish loading device state transferred via the
main migration channel (via save_live_itera
On 2.03.2025 14:00, Avihai Horon wrote:
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Add VFIOStateBuffer(s) types and the associated methods.
These store received device state buffers and config state w
在 2025/3/1 下午3:40, bibo mao 写道:
On 2025/2/28 下午5:06, Song Gao wrote:
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie. we check tlb_ps
when get the tlb_ps f
Change config to show RDT, add minimal code to the rdt.c module to make
sure things still compile.
Signed-off-by: Hendrik Wuethrich
---
hw/i386/Kconfig | 4 ++
hw/i386/meson.build | 1 +
hw/i386/rdt.c | 97 +++
include/hw/i386/rdt.h | 35
Hi Michael,
I guess we're ready to merge this patch series. Patches here have
been thoughfully reviewed mainly by Igor and Jonathan.
The only change from v7 is a minor editorial change at HEST doc
spec, and the addition of Igor and Jonathan's A-B/R-B.
This series change the way HEST table offset
Such file will be used to track HEST table changes.
For now, disallow HEST table check until we update it to the
current data.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
tests/data/acpi/aarch64/virt/HEST | 0
tests/qtest/bios-table
From: Peter Foley
e.g.
Uninitialized value was created by an allocation of 'host_pc' in the stack
frame
#0 0xc07df87c in tb_gen_code
third_party/qemu/accel/tcg/translate-all.c:297:5
Signed-off-by: Peter Foley
Signed-off-by: Patrick Venture
---
accel/tcg/translate-all.c | 2 +-
1 fil
Now that HEST table is checked for aarch64, add the current
firmware file.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
tests/data/acpi/aarch64/virt/HEST | Bin 0 -> 132 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 fil
The current code is actually dependent on having just one error
structure with a single source, as any change there would cause
migration issues.
As the number of sources should be arch-dependent, as it will depend on
what kind of notifications will exist, and how many errors can be
reported at th
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the read ack.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table and the type of the
HEST error blo
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Acked-by: Igor Mammedov
---
hw/acpi/ghes.c | 5 -
include/hw/acpi
Now that we have everything in place, enable using HEST GPA
instead of etc/hardware_errors GPA.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/h
Currently, aarch64 can generate a HEST table when loaded with
-machine ras=on. Add support for it.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add a new ags flag to change the way HEST offsets are calculated.
Currently, offsets needed to store ACPI HEST offsets and read ack
are calculated based on a previous knowledge from the logic
which creates the HEST table.
Such logic is not generic, not allowing to easily add more HEST
entries nor
While the HEST layout didn't change, there are some internal
changes related to how offsets are calculated and how memory error
events are triggered.
Update specs to reflect such changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
docs/sp
Store HEST table address at GPA, placing its the start of the table at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 22 --
include/hw/acpi/ghes.h | 6 +-
2 files change
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
Creates a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU a
Move the check logic into a common function and simplify the
code which checks if GHES is enabled and was properly setup.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes-stub.c| 7 ---
hw/acpi/ghes.c | 38 +
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
This patch series enhances how device IDs are handled in RISC-V IOMMU by
leveraging memory attributes.
The BDF (Bus-Device-Function) is now included in memory attributes for
DMA operations, ensuring accurate device identification.
Since PCIe bus numbers can change after re-enumeration, relying on
This property was originally intended to set the bus number for non-root
endpoints. However, since the PCIe bus number is assigned and modified
at runtime, setting this property before software execution is incorrect.
Additionally, the property incorrectly assumes that all endpoints share
the same
The bus number of a PCIe endpoint may change after PCIe re-enumeration,
potentially causing the device ID stored in RISCVIOMMUSpace to become
outdated. This can lead to an incorrect Device Directory Table walk.
This commit ensures that the IOMMU dynamically retrieves the latest device
IDs from the
This commit adds the BDF to the memory attributes for DMA operations.
Signed-off-by: Jason Chien
---
include/hw/pci/pci_device.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h
index add208edfa..968f1ba3e9 1
The GHES migration logic should now support HEST table location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/gener
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 1e94e1fef5..7b5bb2cd46 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common
@@ -1,39 +1,39 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
- * Disassembly of tests/data/acpi/aarch64/virt/HEST
+ * Disassembly of /tmp/aml-DMPE22
*
* ACPI Data Table [HEST]
*
*
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 10.0 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
We'll be adding a new GED device for HEST GPIO notification and
increasing the number of entries at the HEST table.
Blocklist testing HEST and DSDT tables until such changes
are completed.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
tests/qte
Hi John,
Please take a look at this CI failure:
https://gitlab.com/qemu-project/qemu/-/jobs/9284725716#L150
If you cannot reproduce it locally there is a chance that other pull
requests on the staging branch caused the errors. If that's the case,
please wait for the next update to qemu.git/master
On 2/28/2025 12:30 AM, Francesco Lavra wrote:
On Fri, 2025-01-24 at 08:20 -0500, Xiaoyao Li wrote:
diff --git a/system/runstate.c b/system/runstate.c
index 272801d30769..c4244c8915c6 100644
--- a/system/runstate.c
+++ b/system/runstate.c
@@ -565,6 +565,60 @@ static void qemu_system_wakeup(void)
On 2/28/2025 12:57 AM, Francesco Lavra wrote:
On Fri, 2025-01-24 at 08:20 -0500, Xiaoyao Li wrote:
KVM neithers allow writing to MSR_IA32_APICBASE for TDs, nor allow
for
KVM_SET_LAPIC[*].
Note, KVM_GET_LAPIC is also disallowed for TDX. It is called in the
path
do_kvm_cpu_synchronize_state()
Fabiano
Thanks for your testing.
On 28/02/2025 21:49, Fabiano Rosas wrote:
> Li Zhijian via writes:
>
>> This qtest requires there is a RDMA(RoCE) link in the host.
>> In order to make the test work smoothly, introduce a
>> scripts/rdma-migration-helper.sh to
>> - setup a new Soft-RoCE(aka RXE)
On 3/3/2025 6:00 AM, Dongli Zhang wrote:
Currently, AMD PMU support isn't determined based on CPUID, that is, the
"-pmu" option does not fully disable KVM AMD PMU virtualization.
To minimize AMD PMU features, remove PERFCORE when "-pmu" is configured.
To completely disable AMD PMU virtualizatio
We previously allocate the fifo on reset and never free it, which means
we are leaking memory.
Instead let's allocate on realize and free on unrealize.
Signed-off-by: Alistair Francis
---
hw/char/sifive_uart.c | 44 +++
1 file changed, 28 insertions(+), 1
Hi Cedric,
> Cc: Troy Lee
> Subject: Re: [PATCH v3 01/28] hw/intc/aspeed: Support setting different
> memory and register size
>
> On 2/26/25 04:40, Jamin Lin wrote:
> > Hi Cedric,
> >
> and the register array as:
>
> uint32_t regs[ASPEED_INTC_NR_REGS];
>
> The numb
Hi Cedric,
> Subject: Re: [PATCH v3 15/28] hw/misc/aspeed_scu: Fix the revision ID cannot
> be set in the SOC layer for AST2700
>
> Hello Jamin,
>
> On 2/26/25 07:38, Jamin Lin wrote:
> > Hi Cedric,
> >
> >>
> >> On 2/13/25 04:35, Jamin Lin wrote:
> >>> According to the design of the AST2600, it
AMD does not have what is commonly referred to as an architectural PMU.
Therefore, we need to rename the following variables to be applicable for
both Intel and AMD:
- has_architectural_pmu_version
- num_architectural_pmu_gp_counters
- num_architectural_pmu_fixed_counters
For Intel processors, th
There is no way to distinguish between the following scenarios:
(1) KVM_CAP_PMU_CAPABILITY is not supported.
(2) KVM_CAP_PMU_CAPABILITY is supported but disabled via the module
parameter kvm.enable_pmu=N.
In scenario (1), there is no way to fully disable AMD PMU virtualization.
In scenario (2),
From: Xiaoyao Li
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
The specific implemnet of i386 will be added in the future patch.
Signed-off-by: Xiaoyao Li
Acked-by:
When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is
reflected in in guest dmesg.
[0.285136] Performance Events: AMD PMU driver.
However, the guest CPUID indicates the PerfMonV2 is still available.
CPU:
Extended Performance Monitoring and Debugging (0x8022):
AMD p
The kvm_put_msrs() sets the MSRs using KVM_SET_MSRS. The x86 KVM processes
these MSRs one by one in a loop, only saving the config and triggering the
KVM_REQ_PMU request. This approach does not immediately stop the event
before updating PMC.
In additional, PMU MSRs are set only at levels >= KVM_PU
Although AMD PERFCORE and PerfMonV2 are removed when "-pmu" is configured,
there is no way to fully disable KVM AMD PMU virtualization. Neither
"-cpu host,-pmu" nor "-cpu EPYC" achieves this.
As a result, the following message still appears in the VM dmesg:
[0.263615] Performance Events: AMD
Am 1. März 2025 16:10:35 UTC schrieb BALATON Zoltan :
>On Wed, 15 Jan 2025, BALATON Zoltan wrote:
>> This allows guests to set the CCSR base address. Also store and return
>> values of the local access window registers but their functionality
>> isn't implemented.
>
>Bernhard,
Hi Zoltan,
>
>If
On 2025-02-27 10:17, Peter Maydell wrote:
On Thu, 27 Feb 2025 at 09:15, Sourojeet Adhikari
wrote:
The systmr INTERRUPT_TIMER0..3 sysbus IRQ outputs are already
being wired up in the function bcm_soc_peripherals_common_realize()
in hw/arm/bcm2835_peripherals.c (to the TYPE_BCM2835_IC
interrupt
On 3/2/25 14:00, Avihai Horon wrote:
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Add VFIOStateBuffer(s) types and the associated methods.
These store received device state buffers and config state wait
Hi.
I have interest in contributing patches to extend qemu's powerpc graphics
card emulation to include more comprehensive support for gamma. Some
classic mac applications will balk at launch if the graphics card doesn't
claim enough support for gamma tricks. Native parity should be possible,
allo
The commit 5a99a10da6cf ("target/loongarch: fix vcpu reset command word issue")
fixes the error in the cpu reset ioctl command word delivery process,
so that the command word can be delivered correctly, and adds the judgment
and processing of the error return value, which exposes another problem th
The commit 5a99a10da6cf ("target/loongarch: fix vcpu reset command word issue")
fixes the error in the cpu reset ioctl command word delivery process,
so that the command word can be delivered correctly, and adds the judgment
and processing of the error return value, which exposes another problem th
On 2/25/25 08:56, Jamin Lin wrote:
This patch series is from
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/.
To expedite the review process, I have separated the HACE patches portion from
the
https://patchwork.kernel.org/project/qemu-dev
On Sat, Mar 1, 2025 at 2:36 PM Paolo Bonzini wrote:
>
> On 3/1/25 07:19, Stefan Hajnoczi wrote:
> > Hi,
> > On February 26th GitLab CI started failing many jobs because they
> > could not be scheduled. I've been unable to merge pull requests
> > because the CI is not working.
> >
> > Here is an ex
v1: This patch series is from
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/.
To expedite the review process, I have separated the SCU fix patches
a. Fix the hw-strap and revision ID for SCU and SCUIO
b. ix boot issue for AST2700
Ja
Currently, ASPEED_DEV_SPI_BOOT is set to "0x4", which is the DRAM start
address, and the QEMU loader is used to load the U-Boot binary into this
address.
However, if users want to install FMC flash contents as a boot ROM, the DRAM
address 0x4 would be overwritten with Boot ROM dat
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AS
There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1
register in the SCUIO (IO DIE). The values of these two registers should not be
the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the
SCU and sets the value in the SCU hw-strap1 register, while hw-s
There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1
register in the SCUIO (IO DIE).
In the "ast2700_a0_resets" function, the hardcoded value "0x0800" is set in
SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value
"0x0504" is set in SCUIO hw-stra
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
---
hw/misc/aspeed_scu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc
Separate HW Strap Registers for SCU and SCUIO.
AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1.
AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1.
Additionally, both default values are updated based on the dump from the EVB.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
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From: "Maciej S. Szmigiero"
Maybe add a sentence talking about the load thread itself first? E.g.:
Add a thread which loads the VFIO device state buffers that were
received and via mu
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
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From: "Maciej S. Szmigiero"
Load device config received via multifd using the existing machinery
behind vfio_load_device_config_state().
Also, make sure to process the relevant main mig
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
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From: "Maciej S. Szmigiero"
Implement the multifd device state transfer via additional per-device
thread inside save_live_complete_precopy_thread handler.
Switch between doing the data
On 2.03.2025 15:53, Avihai Horon wrote:
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
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From: "Maciej S. Szmigiero"
Allow capping the maximum count of in-flight VFIO device state buffers
queued at the destination, otherwise a maliciou
On 2.03.2025 15:54, Maciej S. Szmigiero wrote:
On 2.03.2025 15:53, Avihai Horon wrote:
On 19/02/2025 22:34, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Allow capping the maximum count of in-flight VFIO device state buffers
Am 18. Februar 2025 15:54:07 UTC schrieb BALATON Zoltan :
>Add description and set category for eTSEC device so it shows up
>better in -device help.
>
>Signed-off-by: BALATON Zoltan
>---
> hw/net/fsl_etsec/etsec.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/hw/net/fsl_etsec/etsec.c
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