On 2/17/25 04:12, Philippe Mathieu-Daudé wrote:
With this change:
-- >8 --
@@ -678,8 +678,2 @@ static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond,
TCGReg rt,
-static void __attribute__((unused))
-tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm)
-{
- tcg_out
Add MEM_READ/WRITE request to the vhost-user
spec documentation.
Signed-off-by: Albert Esteve
---
docs/interop/vhost-user.rst | 33 +
1 file changed, 33 insertions(+)
diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
index 96156f1900..9f7a2c4
Add new vhost-user protocol
VHOST_USER_PROTOCOL_F_SHMEM feature to
feature map.
Signed-off-by: Albert Esteve
---
hw/virtio/virtio-qmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/virtio/virtio-qmp.c b/hw/virtio/virtio-qmp.c
index 3b6377cf0d..8c2cfd0916 100644
--- a/hw/virtio/virti
Hi all,
v3->v4
- Change mmap strategy to use RAM blocks
and subregions.
- Add new bitfield to qmp feature map
- Followed most review comments from
last iteration.
- Merged documentation patch again with
this one. Makes more sense to
review them together after all.
- Add documentation for M
On Mon, Feb 17, 2025 at 01:23:51PM +, Peter Maydell wrote:
> On Thu, 13 Feb 2025 at 08:44, Kashyap Chamarthy wrote:
> >
> > In v2:
> >
> > - Add live-migration context to the PAuth docs (Marc Zyngier)
> >
> > - Fix the Arm capitlalization (Peter Maydell)
> > - Context here:
> > (
Hi,
First of all sorry for the huge delay, but didn't had time to follow-up
on this lately.
And it got some lower priority, as we don't hit it often and have a
fairly easy workaround (fill the empty blocks again in the snapshot by
writing data to the disk).
On 7/10/24 14:58, Hanna Czenczek w
Hi,
On Mon, Feb 17, 2025 at 02:58:22PM +, Daniel P. Berrangé wrote:
> On Fri, Feb 14, 2025 at 09:29:33PM +0100, Victor Toso wrote:
> > Hi again,
> >
> > This patch series intent is to introduce a generator that produces a Go
> > module for Go applications to interact over QMP with QEMU.
> >
On 2/10/25 12:37 PM, Rob Bradford wrote:
When running in TOR mode (Top of Range) the next PMP entry controls
whether the entry is locked. However simply checking if the PMP_LOCK bit
is set is not sufficient with the Smepmp extension which now provides a
bit (mseccfg.RLB (Rule Lock Bypass)) to
Peter Maydell writes:
> On Fri, 10 Jan 2025 at 13:23, Alex Bennée wrote:
>> Now that we have virtio-gpu Vulkan support, let's add a test for it.
>> Currently this is using images build by buildroot:
>>
>> https://lists.buildroot.org/pipermail/buildroot/2024-December/768196.html
>>
>> Reviewed-
Simplify user implementation of cpu_memory_rw_debug() by
taking the mmap lock globally. See commit 87ab2704296
("linux-user: Allow gdbstub to ignore page protection")
for why this lock is necessary.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 6 -
On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
>
> On a real device, the boot ROM contains the very first instructions the CPU
> executes. Also, U-Boot calls into the ROM to determine the boot device. While
> we're not actually implementing this here, let's create the infrastructure and
> ad
Hi Paolo,
On Sun, 16 Feb 2025 at 14:14, Paolo Bonzini wrote:
>
> On 2/16/25 21:43, Simon Glass wrote:
> > U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it
> > is not perfect.
> >
> > With both builds, executing the VESA ROM causes an intermittent hang, at
> > least on some
On 2/14/25 21:58, Maciej S. Szmigiero wrote:
On 12.02.2025 14:47, Cédric Le Goater wrote:
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different multifd channels can arrive out-of
The 'qapi.backend.QAPIBackend' class defines an API contract for
code generators. The current generator is put into a new class
'qapi.backend.QAPICBackend' and made to be the default impl.
A custom generator can be requested using the '-k' arg which takes
a fully qualified python class name
qa
Dmitry Osipenko writes:
> On 2/17/25 18:22, Alex Bennée wrote:
> ...
>>> This VK_KHR_display problem is only reproducible with your rootfs that
>>> you shared with me. It could be a trouble with your build configs or a
>>> buggy package version used by your rootfs build, more likely the
>>> forme
On 2/12/25 12:29, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 7 +++
1 file changed, 7 insertions(+)
diff --git a/meson.build b/meson.build
index 18cf9e2913b..10f4c9fd30d 100644
--- a/meson.build
+++ b/meson.build
@@ -4826,6 +4826,13 @@ summary_i
On Wed, 12 Feb 2025 at 14:55, Matthew R. Ochs wrote:
>
> The MMIO region size required to support virtualized environments with
> large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
> For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
> requires more MMIO
On 2/17/25 04:50, Peter Maydell wrote:
Because floatx80 has an explicit integer bit, this permits some
odd encodings where the integer bit is not set correctly for the
floating point value type. In In Intel terminology the
categories are:
exp == 0, int = 0, mantissa == 0 : zeroes
exp == 0
From: Hyman Huang
When the developer is examining the time distribution of
the migration, it is useful to record the migration throttle
timestamp. Consequently, include the migration throttle event.
Signed-off-by: Hyman Huang
---
migration/ram.c | 1 +
qapi/migration.json | 15 +++
Write operation with R32 (orig_a0) and R32 (CSR_BADV) is discarded on
gdbstub implementation for LoongArch system. And return value should
be register size rather than 0, since it is used to calculate offset of
next register such as R33 (PC) in function handle_write_all_regs().
Cc: qemu-sta...@non
On 2/13/25 04:35, Jamin Lin wrote:
This method simplifies the process of fetching and extracting assets from the
Aspeed GitHub repository.
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tests/f
On 2025/2/17 上午8:54, Song Gao wrote:
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps, when use
csrwr insn to write CRMD PG=1, check the tlb_ps, and when
use csrwr insn to write STLBPS, check th
On 2/13/25 07:32, Akihiko Odaki wrote:
> On 2025/02/10 6:03, Dmitry Osipenko wrote:
>> On 2/6/25 08:41, Akihiko Odaki wrote:
>>> On 2025/02/06 2:40, Dmitry Osipenko wrote:
On 2/3/25 08:31, Akihiko Odaki wrote:
...
>> Requirements don't vary much. For example virglrenderer minigbm
On 14/02/25 02:08PM, Jonathan Cameron wrote:
On Thu, 13 Feb 2025 14:45:56 +0530
Vinayak Holikatti wrote:
CXL spec 3.1 section 8.2.9.9.5.3 describes media operations commands.
Given the CXL consortium only makes the latest spec available,
generally we try to reference that.
It's move to 8.2.1
On 14/02/25 02:40PM, Jonathan Cameron wrote:
On Thu, 13 Feb 2025 14:45:58 +0530
Vinayak Holikatti wrote:
CXL spec 3.1 section 8.2.9.9.5.3 describes media operations commands.
As in previous - please update to the r3.2 spec.
ok will update as per 3.2
A few comments inline.
Thanks,
Jonatha
On 2/18/25 09:27, Dmitry Osipenko wrote:
>> To be honest, I'm concerned that you may be using QEMU as a staging tree
>> for Mesa/virglrenderer. Submitting a documentation to QEMU as a
>> preparation to submit one to Mesa is not OK.
>>
>> You shouldn't submit a documentation to QEMU if upstream
>> M
On 2/13/25 04:35, Jamin Lin wrote:
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_scu.c | 2 ++
include/hw/misc/aspeed_scu.
On Mon, Feb 17, 2025 at 05:40:04PM +0100, Albert Esteve wrote:
> Add SHMEM_MAP/UNMAP requests to vhost-user to
> handle VIRTIO Shared Memory mappings.
>
> This request allows backends to dynamically map
> fds into a VIRTIO Shared Memory Region indentified
> by its `shmid`. The map is performed by
On Mon, Feb 17, 2025 at 05:40:05PM +0100, Albert Esteve wrote:
> Add missing members to the VhostUserMsg excerpt in
> the vhost-user spec documentation.
>
> Signed-off-by: Albert Esteve
> ---
> docs/interop/vhost-user.rst | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Stefan Hajnoczi
On Tue, Feb 11, 2025 at 1:38 AM Rob Bradford wrote:
>
> When running in TOR mode (Top of Range) the next PMP entry controls
> whether the entry is locked. However simply checking if the PMP_LOCK bit
> is set is not sufficient with the Smepmp extension which now provides a
> bit (mseccfg.RLB (Rule
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "2.2.4. Shadow Stack Pointer"
of `zicfiss` spec
On 1/11/2025 4:08 PM, Stefan Weil via wrote:
Am 10.01.25 um 21:33 schrieb Pierrick Bouvier:
For now, it was only possible to build plugins using GCC on Windows.
However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc_struct attribute, which
is not
supported
Hello Jamin,
On 2/13/25 04:35, Jamin Lin wrote:
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes
On 2/13/25 04:35, Jamin Lin wrote:
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functio
"addr & 0x18" ignores invalid address, so that the trace in default
branch (trace_hpet_ram_{read|write}_invalid()) doesn't work.
Mask addr by "0x1f & ~4", in which 0x1f means to get the complete TN
registers access and ~4 means to keep any invalid address offset.
Signed-off-by: Zhao Liu
---
* N
Hi Zhenzhong,
On 2/18/25 4:32 AM, Duan, Zhenzhong wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Subject: [PATCH v2 0/5] Fix vIOMMU reset order
>>
>> With current reset scheme, DMA capable devices are reset before
> s/before/after
ugh definitively! :-)
>
>> the vIOMMU wh
On Tue, Feb 11, 2025 at 1:38 AM Rob Bradford wrote:
>
> When running in TOR mode (Top of Range) the next PMP entry controls
> whether the entry is locked. However simply checking if the PMP_LOCK bit
> is set is not sufficient with the Smepmp extension which now provides a
> bit (mseccfg.RLB (Rule
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a zimop like other shadow stack instructions).
If shadow stack is not enabled (via xenvcfg.SSE), then `ssamoswap` must
result
On Wed, Feb 12, 2025 at 03:27:26PM +0100, Hanna Czenczek wrote:
> On 12.02.25 14:26, Kevin Wolf wrote:
> > Am 12.02.2025 um 10:32 hat Hanna Czenczek geschrieben:
> > > RBD schedules the request completion code (qemu_rbd_finish_bh()) to run
> > > in the BDS's AioContext. The intent seems to be to r
On 2/13/25 04:35, Jamin Lin wrote:
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
Revie
On 2/13/25 04:35, Jamin Lin wrote:
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
On 2/13/25 04:35, Jamin Lin wrote:
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support t
1)get alert configuration(Opcode 4201h)
2)set alert configuration(Opcode 4202h)
The patch is generated against the Johnathan's tree
https://gitlab.com/jic23/qemu.git and branch cxl-2024-11-27.
Signed-off-by: Sweta Kumari
---
Changes in V2:
- Removed cover letter as it's a single patch
- Added la
On 2/13/25 04:35, Jamin Lin wrote:
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-
On 2/13/25 04:35, Jamin Lin wrote:
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modifi
On 2/13/25 04:35, Jamin Lin wrote:
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events
On 2/13/25 04:35, Jamin Lin wrote:
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc
On Tue, Feb 18, 2025 at 3:35 AM Richard Henderson
wrote:
>
> v2: Fix target/loongarch printf formats for vaddr
> Include two more reviewed patches.
>
> This time with actual pull urls. :-/
>
> r~
>
>
> The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
>
> Merge ta
On 2/13/25 04:35, Jamin Lin wrote:
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make the
yong.hu...@smartx.com writes:
> From: Hyman Huang
>
> When the developer is examining the time distribution of
> the migration, it is useful to record the migration throttle
> timestamp. Consequently, include the migration throttle event.
Can you explain what you'd like to do with the informatio
The SoC type name is stored under AspeedSoCClass which is
redundant. Use object_get_typename() instead where needed.
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 1 -
hw/arm/aspeed_ast10x0.c | 3 +--
hw/arm/aspeed_ast2400.c | 4 +---
hw/arm/aspeed_ast2600.c | 3 +
This qtest requirs there is RXE link in the host.
Here is an example to show how to add this RXE link:
$ ./new-rdma-link.sh
192.168.22.93
Signed-off-by: Li Zhijian
---
The RDMA migration was broken again...due to lack of sufficient test/qtest.
It's urgly to add and execute a script to establish
Address an error in RDMA-based migration by ensuring RDMA is prioritized
when saving pages in `ram_save_target_page()`.
Previously, the RDMA protocol's page-saving step was placed after other
protocols due to a refactoring in commit bc38dc2f5f3. This led to migration
failures characterized by unkn
Laurent Vivier writes:
> The netdev reports NETDEV_VHOST_USER_CONNECTED event when
> the chardev is connected, and NETDEV_VHOST_USER_DISCONNECTED
> when it is disconnected.
>
> The NETDEV_VHOST_USER_CONNECTED event includes the chardev id.
>
> This allows a system manager like libvirt to detect w
On 2/17/25 23:13, Maciej S. Szmigiero wrote:
On 17.02.2025 10:38, Cédric Le Goater wrote:
On 2/14/25 21:55, Maciej S. Szmigiero wrote:
On 12.02.2025 11:55, Cédric Le Goater wrote:
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data struc
On 14/02/2025 01:59, Fabiano Rosas wrote:
> Remove all instances of _fd_ from the migration generic code. These
> functions have grown over time and the _fd_ part is now just
> confusing.
>
> migration_fd_error() -> migration_error() makes it a little
> vague. Since it's only used for migration_
Roman Penyaev writes:
> This patch implements a new chardev backend `hub` device, which
> aggregates input from multiple backend devices and forwards it to a
> single frontend device. Additionally, `hub` device takes the output
> from the frontend device and sends it back to all the connected
> b
The std::ptr is same as core::ptr, but std has already been used in many
cases and there's no need to choose non-std library.
So, use std::ptr directly to make the used ptr library as consistent as
possible.
Signed-off-by: Zhao Liu
---
rust/hw/char/pl011/src/device.rs | 2 +-
rust/hw/char
Just realized this has been committed already. I'm not complaining, I
was late. Address my doc nits in a followup patch?
On 2/17/25 04:50, Peter Maydell wrote:
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so w
On 2/17/25 6:34 PM, Cédric Le Goater wrote:
> Investigate the git history to uncover when and why the VFIO
> properties were introduced and update the models. This is mostly
> targeting vfio-pci device, since vfio-platform, vfio-ap and vfio-ccw
> devices are simpler.
>
> Sort the properties bas
Am 17. Februar 2025 13:35:04 UTC schrieb Peter Maydell
:
>On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
>>
>> While at it and since they are user-creatable, build them when
>> CONFIG_I2C_DEVICES is set.
>
>The patch subject says this is just a rearrangement
>of the Kconfig stanzas with
Am 16. Oktober 2023 09:05:00 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 5/1/23 16:44, Bernhard Beschow wrote:
>
>> Bernhard Beschow (2):
>>hw/pci-host/bonito: Inline pci_register_root_bus()
>>hw/pci-host/bonito: Map PCI IRQs in board code
>
>Thanks, queued to mips-next.
Ping. I think i
Am 9. Februar 2025 10:36:04 UTC schrieb Bernhard Beschow :
>TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
>itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
>TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
>C
Stefan,
I have yet found a ppc64le Linux distro that has SPI enabled in the
kernel. Attempts to build my own was not successful either. I am trying
to get the LTC (Linux Technology Center) involved. They have more
expertise in building the ppc64le kernel. I am hoping to get that tested
soon.
On Fri, Feb 7, 2025 at 4:27 AM Paolo Bonzini wrote:
>
> To support merging a subclass's RISCVCPUDef into the superclass, a list
> of all the CPU features is needed. Put them into a header file that
> can be included multiple times, expanding the macros BOOL_FIELD and
> TYPE_FIELD to different ope
On Fri, Feb 7, 2025 at 4:29 AM Paolo Bonzini wrote:
>
> Since all TYPE_RISCV_CPU subclasses support a class_data of type
> RISCVCPUDef, process it even before calling the .class_init function
> for the subclasses.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Fri, Feb 7, 2025 at 4:29 AM Paolo Bonzini wrote:
>
> Allow using RISCVCPUDef to replicate all the logic of custom .instance_init
> functions. To simulate inheritance, merge the child's RISCVCPUDef with
> the parent and then finally move it to the CPUState at the end of
> TYPE_RISCV_CPU's own i
On Fri, Feb 7, 2025 at 4:28 AM Paolo Bonzini wrote:
>
> Hi Alastair,
>
> the subject is a slightly underhanded description, in that what I really
> wanted to achieve was removing RISC-V's use of .instance_post_init; that's
> because RISC-V operate with an opposite conception of .instance_post_init
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: [PATCH v2 0/5] Fix vIOMMU reset order
>
>With current reset scheme, DMA capable devices are reset before
s/before/after
>the vIOMMU which translate them. This holds for the different
>IOMMUs and various DMA capable devices such as
On 2/13/25 04:35, Jamin Lin wrote:
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initiali
On 17/02/2025 17.30, Peter Maydell wrote:
On Fri, 10 Jan 2025 at 13:23, Alex Bennée wrote:
Now that we have virtio-gpu Vulkan support, let's add a test for it.
Currently this is using images build by buildroot:
https://lists.buildroot.org/pipermail/buildroot/2024-December/768196.html
Revie
On 2/13/25 04:35, Jamin Lin wrote:
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_res
On Tue, Feb 18, 2025 at 1:44 PM Markus Armbruster wrote:
> yong.hu...@smartx.com writes:
>
> > From: Hyman Huang
> >
> > When the developer is examining the time distribution of
> > the migration, it is useful to record the migration throttle
> > timestamp. Consequently, include the migration th
Hi Zhenzhong,
> -Original Message-
> From: Duan, Zhenzhong
> Sent: Monday, February 17, 2025 9:17 AM
> To: Shameerali Kolothum Thodi
> ; Nicolin Chen
> ; Donald Dutile
> Cc: eric.au...@redhat.com; Peter Maydell ;
> Jason Gunthorpe ; Daniel P. Berrangé
> ; qemu-...@nongnu.org; qemu-
> de.
On 2/13/25 04:35, Jamin Lin wrote:
Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.
Signed-off-by: Jamin Lin
On 2/17/25 09:19, Philippe Mathieu-Daudé wrote:
On 26/1/25 22:16, Richard Henderson wrote:
On 1/23/25 15:44, Philippe Mathieu-Daudé wrote:
CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7
("Use a dedicated function to request exit from execution
loop"), tlb_flush() and tb_flush() are relate
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 75
1 file changed, 23 insertions(+), 52 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host. This shrinks
the size of the structure to 16 bytes on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/tlb-common.h | 10 +-
accel/tc
Since 64-on-32 is now unsupported, guest addresses always
fit in one host register. Drop the replication of opcodes.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 28 ++--
tcg/optimize.c | 21 ++
tcg/tcg-
For loongarch, mips, riscv and sparc, a zero register is
available all the time. For aarch64, register index 31
depends on context: sometimes it is the stack pointer,
and sometimes it is the zero register.
Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined. This
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 15 ++---
tcg/loongarch64/tcg-target-con-str.h | 1 -
tcg/loongarch64/tcg-target.c.inc | 32
3
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 10 +-
tcg/riscv/tcg-target-con-str.h | 1 -
tcg/riscv/tcg-target.c.inc | 28
3 files changed, 17 ins
The declarations use vaddr for size.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 17e2251695..75d075d044 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1
From: Andreas Schwab
SA_RESTORER and the associated sa_restorer field of struct sigaction are
an obsolete feature, not expected to be used by future architectures.
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
defined due to their use of generic/signal.h. This leads to cor
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 62 ++-
1 file changed, 22 insertions(+), 40 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-con-set.h | 26 ++---
tcg/mips/tcg-target-con-str.h | 1 -
tcg/mips/tcg-target.c.inc | 44 ++-
3 files
These should have been removed with the rest. There are
a couple of hosts which can emit guest_base into the
constant pool: aarch64, mips64, ppc64, riscv64.
Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and
TCG_TARGET_NEED_POOL_LABELS")
Signed-off-by: Richard Henderson
Reviewed-
From: Fabiano Rosas
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix by aligning the sta
These defines never should have been added as they were
never used. Only 32-bit hosts may have these opcodes and
they have them unconditionally.
Fixes: 6cb14e4de29 ("tcg/loongarch64: Add the tcg-target.h file")
Fixes: fb1f70f3685 ("tcg/riscv: Add the tcg-target.h file")
Acked-by: Alistair Francis
There is now always only one guest address register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 18 +-
tcg/aarch64/tcg-target.c.inc | 4 ++--
tcg/arm/tcg-target.c.inc | 4 ++--
tcg/i386/tcg-target.c.i
The guest address will now always be TCG_TYPE_I32.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 73 +---
1 file changed, 23 insertions(+), 50 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/
DisasContextBase.pc_next has type vaddr; use the correct log format.
Signed-off-by: Richard Henderson
---
target/loongarch/tcg/translate.c | 2 +-
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/lo
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 56 ++-
1 file changed, 20 insertions(+), 36 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg
v2: Fix target/loongarch printf formats for vaddr
Include two more reviewed patches.
r~
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-con-set.h | 12 ++--
tcg/sparc64/tcg-target-con-str.h | 1 -
tcg/sparc64/tcg-target.c.inc | 17 +++--
3 files changed, 13 insert
From: Mikael Szreder
A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.
Cc: qemu-sta...@nongnu.org
Fixes: 0bba7572d40d ("target/sparc: Perform
From: Artyom Tarasenko
Fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko
Reviewed-by: Ri
Note that 'Z' is still used for addsub2.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 12 -
tcg/aarch64/tcg-target.c.inc | 46 ++--
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/tcg/aarch64/tcg-target-con-set.h
v2: Fix target/loongarch printf formats for vaddr
Include two more reviewed patches.
This time with actual pull urls. :-/
r~
The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging
(2025-02
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