Hi Eric, >-----Original Message----- >From: Eric Auger <eric.au...@redhat.com> >Subject: [PATCH v2 0/5] Fix vIOMMU reset order > >With current reset scheme, DMA capable devices are reset before s/before/after
>the vIOMMU which translate them. This holds for the different >IOMMUs and various DMA capable devices such as virtio devices >and VFIO ones. With virtio devices spurious traces can be >observed at qemu level such as "virtio: zero sized buffers are >not allowed" while for VFIO devices, translation faults can be >observed at host level. > >Virtio devices use 3 phase reset and virtio-pci devices are reset >in the 'hold' phase. VFIO device reset are registered using >qemu_register_reset() and as a consequence they are also reset >on 'hold' phase. > >Note that the tree of QOM devices resets depth-first but it does >so while enforcing the 3 phases. First the tree is traversed doing >the 'enter' phase, then the 'hold' phase and eventually the 'exit' >phase. > >However the QOM hierarchy is not built so that vIOMMUs get reset >before the DMA capable devices (IOMMUs are using either legacy reset s/before/after >scheme or hold phase). Changing the QOM hierarchy does not sound >trivial while forcing the vIOMMUs to be reset on 'exit' phase >sounds reasonable and much simpler. Obviously this relies on the >assumption that all DMA capable devices quiesce their DMA before >(ie. during 'enter' or hold' phase). > >This was tested with qmp system_reset and virsh reset. For the whole series, Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com> Thanks Zhenzhong
