On Fri, Feb 7, 2025 at 4:29 AM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Since all TYPE_RISCV_CPU subclasses support a class_data of type
> RISCVCPUDef, process it even before calling the .class_init function
> for the subclasses.
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 21 ++++++++++-----------
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 803b2a7c3f4..baf4dd017b2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2961,15 +2961,18 @@ static void riscv_cpu_class_base_init(ObjectClass *c,
> void *data)
> } else {
> mcc->def = g_new0(RISCVCPUDef, 1);
> }
> -}
>
> -static void riscv_cpu_class_init(ObjectClass *c, void *data)
> -{
> - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> - RISCVCPUDef *def = data;
> + if (data) {
> + RISCVCPUDef *def = data;
> + if (def->misa_mxl_max) {
> + assert(def->misa_mxl_max <= MXL_RV128);
> + mcc->def->misa_mxl_max = def->misa_mxl_max;
> + }
> + }
>
> - mcc->def->misa_mxl_max = def->misa_mxl_max;
> - riscv_cpu_validate_misa_mxl(mcc);
> + if (!object_class_is_abstract(c)) {
> + riscv_cpu_validate_misa_mxl(mcc);
> + }
> }
>
> static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
> @@ -3069,7 +3072,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_DYNAMIC_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = &((RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> @@ -3080,7 +3082,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_VENDOR_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = &((RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> @@ -3091,7 +3092,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = &((RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> @@ -3102,7 +3102,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
> *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = &((RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> --
> 2.48.1
>
>
