For loongarch, mips, riscv and sparc, a zero register is
available all the time. For aarch64, register index 31
depends on context: sometimes it is the stack pointer,
and sometimes it is the zero register.
Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined. This differs from existing
constant constraints in that const_arg[*] is recorded as
false, indicating that the value is in a register.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg.h | 3 ++-
tcg/aarch64/tcg-target.h | 2 ++
tcg/loongarch64/tcg-target.h | 2 ++
tcg/mips/tcg-target.h | 2 ++
tcg/riscv/tcg-target.h | 2 ++
tcg/sparc64/tcg-target.h | 3 ++-
tcg/tcg.c | 29 ++++++++++++++++++++++-------
docs/devel/tcg-ops.rst | 4 +++-
8 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 1d1d668f52..84d99508b6 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -713,7 +713,8 @@ void tb_target_set_jmp_target(const TranslationBlock *, int,
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
-#define TCG_CT_CONST 1 /* any constant of register size */
+#define TCG_CT_CONST 1 /* any constant of register size */
+#define TCG_CT_REG_ZERO 2 /* zero, in TCG_REG_ZERO */
typedef struct TCGArgConstraint {
unsigned ct : 16;
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 0dd6e1f069..3f3df5176d 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -45,6 +45,8 @@ typedef enum {
TCG_AREG0 = TCG_REG_X19,
} TCGReg;
+#define TCG_REG_ZERO TCG_REG_XZR
+
#define TCG_TARGET_NB_REGS 64
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 8533284631..6a206fb97e 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -85,4 +85,6 @@ typedef enum {
TCG_VEC_TMP0 = TCG_REG_V23,
} TCGReg;
+#define TCG_REG_ZERO TCG_REG_ZERO
+
#endif /* LOONGARCH_TCG_TARGET_H */
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 3090acc4f5..bd4ca5f852 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -70,4 +70,6 @@ typedef enum {
TCG_AREG0 = TCG_REG_S8,
} TCGReg;
+#define TCG_REG_ZERO TCG_REG_ZERO
+
#endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index db5f3d8b72..6dc77d944b 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -57,4 +57,6 @@ typedef enum {
TCG_REG_TMP2 = TCG_REG_T4,
} TCGReg;
+#define TCG_REG_ZERO TCG_REG_ZERO
+
#endif
diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
index f7d75d5806..1b9adccd85 100644
--- a/tcg/sparc64/tcg-target.h
+++ b/tcg/sparc64/tcg-target.h
@@ -64,6 +64,7 @@ typedef enum {
TCG_REG_I7,
} TCGReg;
-#define TCG_AREG0 TCG_REG_I0
+#define TCG_AREG0 TCG_REG_I0
+#define TCG_REG_ZERO TCG_REG_G0
#endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 55cb9b3ac7..e8950df2ad 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3223,6 +3223,11 @@ static void process_constraint_sets(void)
case 'i':
args_ct[i].ct |= TCG_CT_CONST;
break;
+#ifdef TCG_REG_ZERO
+ case 'z':
+ args_ct[i].ct |= TCG_CT_REG_ZERO;
+ break;
+#endif
/* Include all of the target-specific constraints. */
@@ -5074,13 +5079,23 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
arg_ct = &args_ct[i];
ts = arg_temp(arg);
- if (ts->val_type == TEMP_VAL_CONST
- && tcg_target_const_match(ts->val, arg_ct->ct, ts->type,
- op_cond, TCGOP_VECE(op))) {
- /* constant is OK for instruction */
- const_args[i] = 1;
- new_args[i] = ts->val;
- continue;
+ if (ts->val_type == TEMP_VAL_CONST) {
+#ifdef TCG_REG_ZERO
+ if (ts->val == 0 && (arg_ct->ct & TCG_CT_REG_ZERO)) {
+ /* Hardware zero register: indicate register via non-const. */
+ const_args[i] = 0;
+ new_args[i] = TCG_REG_ZERO;
+ continue;
+ }
+#endif
+
+ if (tcg_target_const_match(ts->val, arg_ct->ct, ts->type,
+ op_cond, TCGOP_VECE(op))) {
+ /* constant is OK for instruction */
+ const_args[i] = 1;
+ new_args[i] = ts->val;
+ continue;
+ }
}
reg = ts->reg;
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 6608a29376..688984fd39 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -927,7 +927,9 @@ operation uses a constant input constraint which does not
allow all
constants, it must also accept registers in order to have a fallback.
The constraint '``i``' is defined generically to accept any constant.
The constraint '``r``' is not defined generically, but is consistently
-used by each backend to indicate all registers.
+used by each backend to indicate all registers. If ``TCG_REG_ZERO``
+is defined by the backend, the constraint '``z``' is defined generically
+to map constant 0 to the hardware zero register.
The movi_i32 and movi_i64 operations must accept any constants.
--
2.43.0
