RE: [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before IOMMU reset

Hi Eric, >-Original Message- >From: Eric Auger >Subject: [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before >IOMMU reset > >From: Peter Xu > >No bug report for this, but logically tearing down of existing address >space should happen before reset of IOMMU state / registers,

[PATCH v3 010/162] tcg: Convert andc to TCGOutOpBinary

At the same time, drop all backend support for immediate operands, as we now transform andc to and during optimize. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-con-set.h| 2 +- tcg/i3

[PATCH v3 026/162] tcg: Merge INDEX_op_nor_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 -- tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci

[PATCH v3 020/162] tcg: Convert eqv to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-has.h | 2 -- tcg/riscv

[PATCH v3 068/162] tcg: Merge INDEX_op_muls2_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 + tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.in

[PATCH v3 012/162] tcg: Convert or to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 +++ tcg/aarch64/tcg-target.c.inc | 31 - tcg/arm/tcg-target.c.inc | 24 tcg/i386/tcg-target.c.inc| 25 + tcg/loongarch64/tcg-target.c.inc | 29 +

[PATCH v3 031/162] tcg: Merge INDEX_op_neg_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 30 ++ tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 11 +-- docs/deve

[PATCH v3 039/162] tcg: Merge INDEX_op_mulsh_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 8 tcg/tcg.c | 14 -- docs/devel/tcg-ops.rst | 2 +- 5 files changed, 15 insertions(+), 22 deletions(-) diff --git a/include/

[PATCH v3 041/162] tcg: Merge INDEX_op_div_{i32,i64}

Rename to INDEX_op_divs to emphasize signed inputs, and mirroring INDEX_op_divu_*. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 +++- tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c

[PATCH v3 048/162] tcg: Convert rem to TCGOutOpBinary

For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 -- tcg/tci.c| 4 ++-- tcg/aarch64/tcg-target.c.inc | 19 ++

[PATCH v3 033/162] tcg: Merge INDEX_op_not_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 13 ++--- tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 11 +-- docs/devel/tcg

[PATCH v3 018/162] tcg: Merge INDEX_op_xor_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- target/sh4/translate.c | 6 +++--- tcg/optimize.c | 18 -- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 9 +++-- tcg/tci.c

[PATCH v3 044/162] tcg: Convert div2 to TCGOutOpDivRem

Signed-off-by: Richard Henderson --- tcg/tcg.c| 24 +++-- tcg/aarch64/tcg-target.c.inc | 4 +++ tcg/arm/tcg-target.c.inc | 4 +++ tcg/i386/tcg-target.c.inc| 17 tcg/loongarch64/tcg-target.c.inc | 4 +++ tcg/mips/tcg-target.c.

[PATCH v3 053/162] tcg: Merge INDEX_op_shl_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 13 - docs/devel/tcg-ops.rst | 4 ++-- tcg/tci/tcg-target.c.inc |

[PATCH v3 035/162] tcg: Merge INDEX_op_mul_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 4 ++-- tcg/tcg-op.c | 12 ++-- tcg/tcg.c| 14 ++ tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc |

[PATCH v3 064/162] tcg: Merge INDEX_op_ctz_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc |

[PATCH v3 058/162] tcg: Do not require both rotr and rotl from the backend

Many host architectures do not implement both rotate right and rotate left and require the compiler to negate the shift count to rotate the opposite direction. We have been requiring the backend to perform this transformation. Do this during opcode expansion so that the next patch can drop support

[PATCH v3 003/162] tcg: Merge INDEX_op_mov_{i32,i64}

Begin to rely on TCGOp.type to discriminate operations, rather than two different opcodes. Convert mov first. Introduce TCG_OPF_INT in order to keep opcode dumps the same. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 ++-- inclu

[PATCH v3 078/162] tcg: Merge INDEX_op_brcond_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 6 +++--- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 24 tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.i

[PATCH v3 073/162] tcg/tci: Support negsetcond

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-has.h | 4 ++-- tcg/tci/tcg-target.c.inc | 13 + 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index 2402889bec..7787347e05 100644 --- a/tcg/tci/tcg-target-ha

Re: [PATCH 0/4] target/arm: Improvement on memory error handling

On 2/14/25 7:53 PM, Jonathan Cameron wrote: On Fri, 14 Feb 2025 14:16:31 +1000 Gavin Shan wrote: Currently, there is only one CPER buffer (entry), meaning only one memory error can be reported. In extreme case, multiple memory errors can be raised on different vCPUs. For example, a singile mem

Re: [PATCH 2/2] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64

On Sun, Feb 16, 2025 at 12:49 PM Richard Henderson wrote: > > These defines never should have been added as they were > never used. Only 32-bit hosts may have these opcodes and > they have them unconditionally. > > Signed-off-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- >

Re: [PATCH 5/5] hw/riscv: Configurable MPFS CLINT timebase freq

On 14/2/25 07:24, Sebastian Huber wrote: This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 49

[PATCH v3 056/162] tcg: Convert sar to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++- tcg/aarch64/tcg-target.c.inc | 37 - tcg/arm/tcg-target.c.inc | 26 tcg/i386/tcg-target.c.inc| 46 - tcg/loongarch64/tcg-target.c.inc | 43 +

[PATCH v3 112/162] tcg: Add add/sub with carry opcodes and infrastructure

Liveness needs to track carry-live state in order to determine if the (hidden) output of the opcode is used. Code generation needs to track carry-live state in order to avoid clobbering cpu flags when loading constants. So far, output routines and backends are unchanged. Signed-off-by: Richard He

[PATCH v3 011/162] tcg: Merge INDEX_op_andc_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- target/arm/tcg/translate-a64.c | 2 +- target/tricore/translate.c | 2 +- tcg/optimize.c | 6 -- tcg/tcg-op.c | 8 tcg/tcg.c

[PATCH v3 090/162] tcg: Convert bswap64 to TCGOutOpUnary

Use TCGOutOpUnary instead of TCGOutOpBswap because the flags are not used with this opcode; they are merely present for uniformity with the smaller bswaps. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 1 - tcg/loongarch64/tcg-t

[PATCH v3 054/162] tcg: Convert shr to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 +++-- tcg/aarch64/tcg-target.c.inc | 37 ++- tcg/arm/tcg-target.c.inc | 24 ++ tcg/i386/tcg-target.c.inc| 33 +++- tcg/loongarch64/tcg-target

[PATCH v3 119/162] tcg/i386: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 86 --- 1 file changed, 72 insertions(+), 14 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cbe67102aa..524e288f26 100644 --- a/tcg/i386/tcg-target.c.inc ++

[PATCH v3 040/162] tcg: Convert div to TCGOutOpBinary

For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 8 +++--- tcg/tcg.c| 6 +++-- tcg/tci.c| 3 ++- tcg/aarc

[PATCH v3 123/162] target/arm: Use tcg_gen_addcio_* for ADCS

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 8 ++-- target/arm/tcg/translate.c | 17 +++-- 2 files changed, 5 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7587cad923..898382be85 10

[PATCH v3 038/162] tcg: Convert mulsh to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-has.h | 2 -- tcg/riscv

[PATCH v3 157/162] tcg: Stash MemOp size in TCGOP_FLAGS

This will enable removing INDEX_op_qemu_st8_*_i32, by exposing the operand size to constraint selection. Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 73838e2701..b087

[PATCH v3 066/162] tcg: Merge INDEX_op_ctpop_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 9 +++-- tcg/tcg-op.c | 21 ++--- tcg/tcg.c| 6 ++ tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst | 6 +++--- tcg/tci/tcg-targe

[PATCH v3 070/162] tcg: Merge INDEX_op_mulu2_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 + tcg/tcg-op.c | 10 +- tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.

[PATCH v3 131/162] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC

Signed-off-by: Richard Henderson --- target/tricore/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5ae685cc5b..2036ac2cd6 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c

[PATCH v3 105/162] tcg: Expand fallback add2 with 32-bit operations

No need to expand to i64 to perform the add. This may smaller on a loongarch64 host, e.g. bstrpick_d r28, r27, 31, 0 bstrpick_d r29, r24, 31, 0 add_d r28, r28, r29 addi_w r29, r28, 0 srai_d r28, r28, 32 --- add_w r28, r27, r

[PATCH v3 122/162] tcg: Add tcg_gen_addcio_{i32,i64,tl}

Create a function for performing an add with carry-in and producing carry out. The carry-out result is boolean. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 4 ++ include/tcg/tcg-op.h| 2 + tcg/tcg-op.c| 95 + 3

[PATCH v3 063/162] tcg: Convert ctz to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-has.h | 2 -- tcg/riscv

[PATCH v3 153/162] tcg: Convert ld to TCGOutOpLoad

Signed-off-by: Richard Henderson --- tcg/tcg.c| 46 +++ tcg/aarch64/tcg-target.c.inc | 113 --- tcg/arm/tcg-target.c.inc | 126 --- tcg/i386/tcg-target.c.inc| 112 ---

[PATCH v3 147/162] tcg/tci: Remove support for add2/sub2

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-has.h | 8 ++--- tcg/tci.c| 66 +++- tcg/tci/tcg-target.c.inc | 28 - 3 files changed, 9 insertions(+), 93 deletions(-) diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg

[PATCH v3 146/162] tcg/tci: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/tci.c| 54 tcg/tci/tcg-target-opc.h.inc | 1 + tcg/tci/tcg-target.c.inc | 69 +++- 3 files changed, 116 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c

[PATCH v3 132/162] tcg/aarch64: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 + tcg/aarch64/tcg-target.c.inc | 152 +-- 2 files changed, 146 insertions(+), 8 deletions(-) diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h index 2eda499

[PATCH v3 107/162] tcg: Do not default add2/sub2_i32 for 32-bit hosts

Require TCG_TARGET_HAS_{add2,sub2}_i32 be defined, one way or another. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-has.h | 2 ++ tcg/mips/tcg-target-has.h | 3 +++ tcg/ppc/tcg-target-has.h | 3 +++ tcg/tcg-has.h | 3 --- tcg/tci/tcg-target-has.h | 4 ++-- 5 files chang

[PATCH v3 126/162] target/openrisc: Use tcg_gen_addcio_* for ADDC

Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7a6af183ae..c9856fdc88 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c

[PATCH v3 059/162] tcg: Convert rotl, rotr to TCGOutOpBinary

For aarch64, arm, loongarch64, mips, we can drop rotl. For ppc, s390x we can drop rotr. Only x86, riscv (and tci) have both rotl and rotr. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2

[PATCH v3 060/162] tcg: Merge INDEX_op_rot{l,r}_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 6 ++--- tcg/optimize.c | 20 - tcg/tcg-op.c | 48 tcg/tcg.c| 12 -- tcg/tci.c| 8 +++ docs/devel/tcg-ops.rs

[PATCH v3 046/162] tcg: Convert divu2 to TCGOutOpDivRem

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/riscv/tcg-target-has.h | 2 -- tcg/s390x/tcg-target-has.h | 2 -- tcg/tcg-has.h| 7 --- tcg/tcg-op.c | 8 +++

[PATCH v3 081/162] tcg/ppc: Drop fallback constant loading in tcg_out_cmp

Use U and C constraints for brcond2 and setcond2, so that tcg_out_cmp2 automatically passes in-range constants to tcg_out_cmp. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 4 +-- tcg/ppc/tcg-target.c.inc | 49 2 files changed, 18 i

[PATCH v3 114/162] tcg/optimize: Handle add/sub with carry opcodes

Propagate known carry when possible, and simplify the opcodes to not require carry-in when known. The result will be cleaned up further by the subsequent liveness analysis pass. Signed-off-by: Richard Henderson --- tcg/optimize.c | 319 - 1 file c

[PATCH v3 115/162] tcg/optimize: With two const operands, prefer 0 in arg1

For most binary operands, two const operands fold. However, the add/sub carry opcodes have a third input. Prefer "reg, zero, const" since many risc hosts have a zero register that can fit a "reg, reg, const" insn format. --- tcg/optimize.c | 18 -- 1 file changed, 12 insertions(+),

[PATCH v3 095/162] tcg: Merge INDEX_op_sextract_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 22 +++--- tcg/tcg-op.c | 12 ++-- tcg/tcg.c| 9 +++-- tcg/tci.c| 12 docs/devel/tcg-ops.rst | 2 +- tcg/tci/

[PATCH v3 089/162] tcg: Merge INDEX_op_bswap32_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 13 ++--- tcg/tci/tcg-target.c.i

[PATCH v3 077/162] tcg: Convert brcond to TCGOutOpBrcond

Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/mips/tcg-target-con-set.h| 4 +-- tcg/riscv/tcg-target-con-set.h | 2 +- tcg/sparc64/tcg-target-con-set.h | 2 +- tcg/tcg.c| 26 +++ tcg/tci.c

[PATCH v3 108/162] tcg/mips: Drop support for add2/sub2

We now produce exactly the same code via generic expansion. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 1 - tcg/mips/tcg-target-con-str.h | 1 - tcg/mips/tcg-target-has.h | 7 ++-- tcg/mips/tcg-target.c.inc | 67 +-- 4 files ch

[PATCH v3 143/162] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc

Pass the sparc COND_* value not the tcg TCG_COND_* value. This makes the usage within add2/sub2 clearer. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tc

[PATCH v3 136/162] tcg/ppc: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 3 + tcg/ppc/tcg-target-con-str.h | 1 + tcg/ppc/tcg-target.c.inc | 167 ++- 3 files changed, 150 insertions(+), 21 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-tar

[PATCH v3 151/162] tcg: Formalize tcg_out_goto_ptr

Split these functions out from tcg_out_op. Define outop_goto_ptr generically. Call tcg_out_goto_ptr from tcg_reg_alloc_op. Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 tcg/aarch64/tcg-target.c.inc | 12 +--- tcg/arm/tcg-target.c.inc

[PATCH v3 087/162] tcg: Merge INDEX_op_bswap16_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 7 files

[PATCH v3 047/162] tcg: Merge INDEX_op_divu2_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.rst | 10 ++ 4 files changed, 21 insertions(+), 14 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-

[PATCH v3 023/162] tcg: Merge INDEX_op_nand_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 -- tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci

[PATCH v3 088/162] tcg: Convert bswap32 to TCGOutOpBswap

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h | 2 - tcg/riscv/tcg-

[PATCH v3 075/162] tcg: Convert setcond, negsetcond to TCGOutOpSetcond

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h| 2 +- tcg/sparc64/tcg-target-con-set.h | 1 - tcg/tcg.c| 31 tcg/aarch64/tcg-target.c.inc | 121 --- tcg/arm/tcg-target.c.inc | 117 +++

[PATCH v3 072/162] tcg/mips: Support negsetcond

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-has.h | 4 ++-- tcg/mips/tcg-target.c.inc | 25 + 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index 05701fd228..c77d4296cf 100644 --- a/tcg/m

[PATCH v3 156/162] tcg: Merge INDEX_op_st*_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 15 -- tcg/optimize.c | 28 +++-- tcg/tcg-op.c | 14 ++--- tcg/tcg.c| 45 +--- tcg/tci.c| 36 +-

[PATCH v3 093/162] tcg: Merge INDEX_op_extract_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 14 -- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 12 docs/devel/tcg-ops.rst | 6 +++--- tcg/tci/tcg-targ

[PATCH v3 154/162] tcg: Merge INDEX_op_ld*_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 19 +--- tcg/optimize.c | 27 - tcg/tcg-op.c | 24 +++ tcg/tcg.c| 64 ++-- tcg/tci.c| 43 +++---

[PATCH v3 021/162] tcg: Merge INDEX_op_eqv_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 -- tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci

[PATCH v3 055/162] tcg: Merge INDEX_op_shr_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 +++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 11 +++ docs/devel/tcg-ops.rst | 4 ++-- tcg/tci/tcg-target.c.in

[PATCH v3 116/162] tcg: Use add carry opcodes to expand add2

Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 127338b994..f17ec658fb 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1102,7 +1102,13 @@ void tcg_gen_movcond_i3

[PATCH v3 124/162] target/hppa: Use tcg_gen_addcio_i64

Use this in do_add, do_sub, and do_ds, all of which need add with carry-in and carry-out. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0d

[PATCH v3 149/162] tcg: Formalize tcg_out_mb

Most tcg backends already have a function for this; the rest can split one out from tcg_out_op. Call it directly from tcg_gen_code. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 6 +- tcg/arm/tcg-target.c.inc | 6

[PATCH v3 134/162] tcg/arm: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 2 + tcg/arm/tcg-target.c.inc | 165 +-- 2 files changed, 159 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index f46a8444fb..a44625b

[PATCH v3 091/162] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64

Even though bswap64 can only be used with TCG_TYPE_I64, rename the opcode to maintain uniformity. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 +++--- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 +++--- tcg/tci.c

[PATCH v3 079/162] tcg: Convert movcond to TCGOutOpMovcond

Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/mips/tcg-target-con-set.h| 3 ++- tcg/s390x/tcg-target-con-set.h | 1 - tcg/sparc64/tcg-target-con-set.h | 2 +- tcg/tcg.c| 23 +++ tcg/tci.c

[PATCH v3 071/162] tcg/loongarch64: Support negsetcond

Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-has.h | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 34 ++-- 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/tcg/loongarch64/tcg-target-co

[PATCH v3 117/162] tcg: Use sub carry opcodes to expand sub2

Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f17ec658fb..447b0ebacd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1126,7 +1126,13 @@ void tcg_gen_add2_i32(T

[PATCH v3 160/162] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}

Signed-off-by: Richard Henderson --- tcg/tcg.c| 32 +++- tcg/aarch64/tcg-target.c.inc | 30 +-- tcg/arm/tcg-target.c.inc | 63 +++- tcg/i386/tcg-target.c.inc| 47 tcg/loongarch

[PATCH v3 080/162] tcg: Merge INDEX_op_movcond_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 2 +- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 15 +-- tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 7 fi

[PATCH v3 109/162] tcg/riscv: Drop support for add2/sub2

We now produce exactly the same code via generic expansion. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target-has.h | 6 +-- tcg/riscv/tcg-target.c.inc | 86 +- 3 files changed, 3 insertions(+), 90 deletions(

[PATCH v3 102/162] tcg: Merge INDEX_op_deposit_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 2 +- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst | 6 -- tcg/tci/tcg-target.c.inc | 2 +- 7 files

[PATCH v3 161/162] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}

Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 - tcg/aarch64/tcg-target.c.inc | 45 --- tcg/arm/tcg-target.c.inc | 61 - tcg/i386/tcg-target.c.inc| 71 - tcg/loongarch64/tcg-ta

[PATCH v3 162/162] tcg: Remove tcg_out_op

All integer opcodes are now converted to TCGOutOp. Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 +++- tcg/aarch64/tcg-target.c.inc | 7 --- tcg/arm/tcg-target.c.inc | 7 --- tcg/i386/tcg-target.c.inc| 7 --- tcg/loongarch64

[PATCH v3 086/162] tcg: Convert bswap16 to TCGOutOpBswap

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h | 2 - tcg/riscv/tcg-

[PATCH v3 103/162] tcg: Convert extract2 to TCGOutOpExtract2

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 6 - tcg/ppc/tcg-target-has.h | 2 -- tcg/ri

[PATCH v3 137/162] tcg/ppc: Remove support for add2/sub2

We have replaced this with support for add/sub carry. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 2 -- tcg/ppc/tcg-target-has.h | 11 +++ tcg/ppc/tcg-target.c.inc | 60 3 files changed, 4 insertions(+), 69 deletions(-) d

[PATCH v3 094/162] tcg: Convert sextract to TCGOutOpExtract

Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 ++ tcg/aarch64/tcg-target.c.inc | 18 + tcg/arm/tcg-target.c.inc | 21 ++- tcg/i386/tcg-target.c.inc| 63 tcg/loongarch64/tcg-target.c.inc | 49

[PATCH v3 101/162] tcg/aarch64: Improve deposit

Use ANDI for deposit 0 into a register. Use UBFIZ, aka UBFM, for deposit register into 0. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 +- tcg/aarch64/tcg-target.c.inc | 29 - 2 files changed, 29 insertions(+), 2 deletions(-) diff --

[PATCH v3 061/162] tcg: Convert clz to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h | 2 - tcg/risc

[PATCH v3 043/162] tcg: Merge INDEX_op_divu_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 9 + tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc |

[PATCH v3 069/162] tcg: Convert mulu2 to TCGOutOpMul2

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-has.h | 2 -- tcg/riscv

[PATCH v3 034/162] tcg: Convert mul to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++- tcg/aarch64/tcg-target.c.inc | 18 --- tcg/arm/tcg-target.c.inc | 23 tcg/i386/tcg-target.c.inc| 47 +--- tcg/loongarch64/tcg-target.c.inc | 24 + tcg/mips/tcg-targ

[PATCH v3 121/162] tcg/i386: Special case addci r, 0, 0

Using addci with two zeros as input in order to capture the value of the carry-in bit is common. Special case this with sbb+neg so that we do not have to load 0 into a register first. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 1 + tcg/i386/tcg-target.c.inc | 46 +

[PATCH v3 019/162] tcg/optimize: Fold eqv with immediate to xor

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index a4dc88ae71..a49d51f0d7 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@

[PATCH v3 128/162] target/s390x: Use tcg_gen_addcio_i64 for op_addc64

Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 00073c5560..a714f9c0c2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/tran

[PATCH v3 065/162] tcg: Convert ctpop to TCGOutOpUnary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h | 2 - tcg/riscv/tcg-

[PATCH v3 052/162] tcg: Convert shl to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++-- tcg/aarch64/tcg-target.c.inc | 38 ++-- tcg/arm/tcg-target.c.inc | 25 + tcg/i386/tcg-target.c.inc| 60 +++- tcg/loongarch64/tcg-target.c.in

[PATCH v3 025/162] tcg: Convert nor to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-has.h | 2 -- tcg/riscv

[PATCH v3 051/162] tcg: Merge INDEX_op_remu_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 5 + tcg/optimize.c | 9 + tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 7 files

[PATCH v3 150/162] tcg: Formalize tcg_out_br

Split these functions out from tcg_out_op. Call it directly from tcg_gen_code. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 6 +- tcg/arm/tcg-target.c.inc | 8 +--- tcg/i386/tcg-target.c.inc| 8

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