Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 3 +--
tcg/tcg-op.c | 16 ++++++++--------
tcg/tcg.c | 6 ++----
docs/devel/tcg-ops.rst | 10 ++++++++++
4 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 36dfbf80ad..61e5e185cc 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -45,6 +45,7 @@ DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(divs, 1, 2, 0, TCG_OPF_INT)
DEF(divs2, 2, 3, 0, TCG_OPF_INT)
DEF(divu, 1, 2, 0, TCG_OPF_INT)
+DEF(divu2, 2, 3, 0, TCG_OPF_INT)
DEF(eqv, 1, 2, 0, TCG_OPF_INT)
DEF(mul, 1, 2, 0, TCG_OPF_INT)
DEF(mulsh, 1, 2, 0, TCG_OPF_INT)
@@ -73,7 +74,6 @@ DEF(st_i32, 0, 2, 1, 0)
/* arith */
DEF(rem_i32, 1, 2, 0, 0)
DEF(remu_i32, 1, 2, 0, 0)
-DEF(divu2_i32, 2, 3, 0, 0)
/* shifts/rotates */
DEF(shl_i32, 1, 2, 0, 0)
DEF(shr_i32, 1, 2, 0, 0)
@@ -118,7 +118,6 @@ DEF(st_i64, 0, 2, 1, 0)
/* arith */
DEF(rem_i64, 1, 2, 0, 0)
DEF(remu_i64, 1, 2, 0, 0)
-DEF(divu2_i64, 2, 3, 0, 0)
/* shifts/rotates */
DEF(shl_i64, 1, 2, 0, 0)
DEF(shr_i64, 1, 2, 0, 0)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 5511106554..7ed92157de 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -637,10 +637,10 @@ void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1,
TCGv_i32 arg2)
{
if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_divu, ret, arg1, arg2);
- } else if (tcg_op_supported(INDEX_op_divu2_i32, TCG_TYPE_I32, 0)) {
+ } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 zero = tcg_constant_i32(0);
- tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, zero, arg2);
+ tcg_gen_op5_i32(INDEX_op_divu2, ret, t0, arg1, zero, arg2);
tcg_temp_free_i32(t0);
} else {
gen_helper_divu_i32(ret, arg1, arg2);
@@ -657,10 +657,10 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1,
TCGv_i32 arg2)
tcg_gen_mul_i32(t0, t0, arg2);
tcg_gen_sub_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
- } else if (tcg_op_supported(INDEX_op_divu2_i32, TCG_TYPE_I32, 0)) {
+ } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 zero = tcg_constant_i32(0);
- tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, zero, arg2);
+ tcg_gen_op5_i32(INDEX_op_divu2, t0, ret, arg1, zero, arg2);
tcg_temp_free_i32(t0);
} else {
gen_helper_remu_i32(ret, arg1, arg2);
@@ -2005,10 +2005,10 @@ void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2)
{
if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_divu, ret, arg1, arg2);
- } else if (tcg_op_supported(INDEX_op_divu2_i64, TCG_TYPE_I64, 0)) {
+ } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 zero = tcg_constant_i64(0);
- tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, zero, arg2);
+ tcg_gen_op5_i64(INDEX_op_divu2, ret, t0, arg1, zero, arg2);
tcg_temp_free_i64(t0);
} else {
gen_helper_divu_i64(ret, arg1, arg2);
@@ -2025,10 +2025,10 @@ void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2)
tcg_gen_mul_i64(t0, t0, arg2);
tcg_gen_sub_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
- } else if (tcg_op_supported(INDEX_op_divu2_i64, TCG_TYPE_I64, 0)) {
+ } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 zero = tcg_constant_i64(0);
- tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, zero, arg2);
+ tcg_gen_op5_i64(INDEX_op_divu2, t0, ret, arg1, zero, arg2);
tcg_temp_free_i64(t0);
} else {
gen_helper_remu_i64(ret, arg1, arg2);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 43122a97c6..560755bad8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1029,8 +1029,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs),
OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu),
OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2),
- OUTOP(INDEX_op_divu2_i32, TCGOutOpDivRem, outop_divu2),
- OUTOP(INDEX_op_divu2_i64, TCGOutOpDivRem, outop_divu2),
+ OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
@@ -5459,8 +5458,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
break;
case INDEX_op_divs2:
- case INDEX_op_divu2_i32:
- case INDEX_op_divu2_i64:
+ case INDEX_op_divu2:
{
const TCGOutOpDivRem *out =
container_of(all_outop[op->opc], TCGOutOpDivRem, base);
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 62af390854..8f3b5e91b2 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -307,6 +307,16 @@ Arithmetic
pass *nh* as a simple sign-extension of *nl*, so the only
overflow should be *INT_MIN* / -1.
+ * - divu2 *q*, *r*, *nl*, *nh*, *d*
+
+ - | *q* = *nh:nl* / *d* (unsigned)
+ | *r* = *nh:nl* % *d*
+ | Undefined behaviour if division by zero, or the double-word
+ numerator divided by the single-word divisor does not fit
+ within the single-word quotient. The code generator will
+ pass 0 to *nh* to make a simple zero-extension of *nl*,
+ so overflow should never occur.
+
Logical
-------
--
2.43.0
