Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 3 +--
tcg/optimize.c | 10 +++++-----
tcg/tcg-op.c | 8 ++++----
tcg/tcg.c | 14 ++++----------
docs/devel/tcg-ops.rst | 2 +-
5 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 28a5128537..a9d7938a52 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -44,6 +44,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(eqv, 1, 2, 0, TCG_OPF_INT)
DEF(mul, 1, 2, 0, TCG_OPF_INT)
+DEF(mulsh, 1, 2, 0, TCG_OPF_INT)
DEF(muluh, 1, 2, 0, TCG_OPF_INT)
DEF(nand, 1, 2, 0, TCG_OPF_INT)
DEF(neg, 1, 1, 0, TCG_OPF_INT)
@@ -90,7 +91,6 @@ DEF(add2_i32, 2, 4, 0, 0)
DEF(sub2_i32, 2, 4, 0, 0)
DEF(mulu2_i32, 2, 2, 0, 0)
DEF(muls2_i32, 2, 2, 0, 0)
-DEF(mulsh_i32, 1, 2, 0, 0)
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(setcond2_i32, 1, 4, 1, 0)
@@ -151,7 +151,6 @@ DEF(add2_i64, 2, 4, 0, 0)
DEF(sub2_i64, 2, 4, 0, 0)
DEF(mulu2_i64, 2, 2, 0, 0)
DEF(muls2_i64, 2, 2, 0, 0)
-DEF(mulsh_i64, 1, 2, 0, 0)
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index cd37a540ca..f8d9a4d90e 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -537,10 +537,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op,
TCGType type,
mulu64(&l64, &h64, x, y);
return h64;
- case INDEX_op_mulsh_i32:
- return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
-
- case INDEX_op_mulsh_i64:
+ case INDEX_op_mulsh:
+ if (type == TCG_TYPE_I32) {
+ return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
+ }
muls64(&l64, &h64, x, y);
return h64;
@@ -2957,7 +2957,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_mul:
done = fold_mul(&ctx, op);
break;
- CASE_OP_32_64(mulsh):
+ case INDEX_op_mulsh:
case INDEX_op_muluh:
done = fold_mul_highpart(&ctx, op);
break;
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index a043c4554b..664c698187 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1156,10 +1156,10 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh,
TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_muls2_i32) {
tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
- } else if (tcg_op_supported(INDEX_op_mulsh_i32, TCG_TYPE_I32, 0)) {
+ } else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I32, 0)) {
TCGv_i32 t = tcg_temp_ebb_new_i32();
tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2);
- tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
+ tcg_gen_op3_i32(INDEX_op_mulsh, rh, arg1, arg2);
tcg_gen_mov_i32(rl, t);
tcg_temp_free_i32(t);
} else if (TCG_TARGET_REG_BITS == 32) {
@@ -2861,10 +2861,10 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh,
TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_HAS_muls2_i64) {
tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
- } else if (tcg_op_supported(INDEX_op_mulsh_i64, TCG_TYPE_I64, 0)) {
+ } else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I64, 0)) {
TCGv_i64 t = tcg_temp_ebb_new_i64();
tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2);
- tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);
+ tcg_gen_op3_i64(INDEX_op_mulsh, rh, arg1, arg2);
tcg_gen_mov_i64(rl, t);
tcg_temp_free_i64(t);
} else if (TCG_TARGET_HAS_mulu2_i64 ||
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 22fc90debe..e5d7c3dd19 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1022,8 +1022,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
- OUTOP(INDEX_op_mulsh_i32, TCGOutOpBinary, outop_mulsh),
- OUTOP(INDEX_op_mulsh_i64, TCGOutOpBinary, outop_mulsh),
+ OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh),
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
@@ -4028,18 +4027,14 @@ liveness_pass_1(TCGContext *s)
goto do_not_remove;
case INDEX_op_muls2_i32:
+ case INDEX_op_muls2_i64:
opc_new = INDEX_op_mul;
- opc_new2 = INDEX_op_mulsh_i32;
+ opc_new2 = INDEX_op_mulsh;
goto do_mul2;
case INDEX_op_mulu2_i32:
case INDEX_op_mulu2_i64:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_muluh;
- goto do_mul2;
- case INDEX_op_muls2_i64:
- opc_new = INDEX_op_mul;
- opc_new2 = INDEX_op_mulsh_i64;
- goto do_mul2;
do_mul2:
nb_iargs = 2;
nb_oargs = 2;
@@ -5418,8 +5413,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
case INDEX_op_andc:
case INDEX_op_eqv:
case INDEX_op_mul:
- case INDEX_op_mulsh_i32:
- case INDEX_op_mulsh_i64:
+ case INDEX_op_mulsh:
case INDEX_op_muluh:
case INDEX_op_nand:
case INDEX_op_nor:
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 4fed5a77c6..fe922d1dac 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -589,7 +589,7 @@ Multiword arithmetic support
- | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
- * - mulsh_i32/i64 *t0*, *t1*, *t2*
+ * - mulsh *t0*, *t1*, *t2*
muluh *t0*, *t1*, *t2*
--
2.43.0
