Even though bswap64 can only be used with TCG_TYPE_I64,
rename the opcode to maintain uniformity.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 3 +--
tcg/optimize.c | 6 +++---
tcg/tcg-op.c | 4 ++--
tcg/tcg.c | 6 +++---
tcg/tci.c | 4 ++--
docs/devel/tcg-ops.rst | 5 +++--
tcg/tci/tcg-target.c.inc | 2 +-
7 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 296dffe99a..1d27b882fe 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -45,6 +45,7 @@ DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
+DEF(bswap64, 1, 1, 1, TCG_OPF_INT)
DEF(clz, 1, 2, 0, TCG_OPF_INT)
DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
DEF(ctz, 1, 2, 0, TCG_OPF_INT)
@@ -121,8 +122,6 @@ DEF(extu_i32_i64, 1, 1, 0, 0)
DEF(extrl_i64_i32, 1, 1, 0, 0)
DEF(extrh_i64_i32, 1, 1, 0, 0)
-DEF(bswap64_i64, 1, 1, 1, 0)
-
DEF(add2_i64, 2, 4, 0, 0)
DEF(sub2_i64, 2, 4, 0, 0)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index be9d09467d..87395f8ab5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -514,7 +514,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType
type,
x = bswap32(x);
return y & TCG_BSWAP_OS ? (int32_t)x : x;
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
return bswap64(x);
case INDEX_op_ext_i32_i64:
@@ -1568,7 +1568,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
z_mask = bswap32(z_mask);
sign = INT32_MIN;
break;
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
z_mask = bswap64(z_mask);
sign = INT64_MIN;
break;
@@ -2858,7 +2858,7 @@ void tcg_optimize(TCGContext *s)
break;
case INDEX_op_bswap16:
case INDEX_op_bswap32:
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
done = fold_bswap(&ctx, op);
break;
case INDEX_op_clz:
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 27e700161f..ba062191ac 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2184,8 +2184,8 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- } else if (tcg_op_supported(INDEX_op_bswap64_i64, TCG_TYPE_I64, 0)) {
- tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
+ } else if (tcg_op_supported(INDEX_op_bswap64, TCG_TYPE_I64, 0)) {
+ tcg_gen_op3i_i64(INDEX_op_bswap64, ret, arg, 0);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 t1 = tcg_temp_ebb_new_i64();
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3d3a95367e..0a81a115be 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1113,7 +1113,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2),
OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2),
#else
- OUTOP(INDEX_op_bswap64_i64, TCGOutOpUnary, outop_bswap64),
+ OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64),
#endif
};
@@ -2939,7 +2939,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
break;
case INDEX_op_bswap16:
case INDEX_op_bswap32:
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
{
TCGArg flags = op->args[k];
const char *name = NULL;
@@ -5459,7 +5459,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
}
break;
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
assert(TCG_TARGET_REG_BITS == 64);
/* fall through */
case INDEX_op_ctpop:
diff --git a/tcg/tci.c b/tcg/tci.c
index 903f996f02..30928c3412 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -788,7 +788,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint32_t)regs[r1];
break;
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap64(regs[r1]);
break;
@@ -1009,7 +1009,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_not:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
- case INDEX_op_bswap64_i64:
+ case INDEX_op_bswap64:
tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s",
op_name, str_r(r0), str_r(r1));
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index e89ede54fa..72a23d6ea2 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -431,10 +431,11 @@ Misc
they apply from bit 31 instead of bit 15. On TCG_TYPE_I32, the
flags should be zero.
- * - bswap64_i64 *t0*, *t1*, *flags*
+ * - bswap64 *t0*, *t1*, *flags*
- | 64 bit byte swap. The flags are ignored, but still present
- for consistency with the other bswap opcodes.
+ for consistency with the other bswap opcodes. For future
+ compatibility, the flags should be zero.
* - discard_i32/i64 *t0*
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index cbfe92adf3..4fc857ad35 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -930,7 +930,7 @@ static const TCGOutOpBswap outop_bswap32 = {
#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
- tcg_out_op_rr(s, INDEX_op_bswap64_i64, a0, a1);
+ tcg_out_op_rr(s, INDEX_op_bswap64, a0, a1);
}
static const TCGOutOpUnary outop_bswap64 = {
--
2.43.0
