[PATCH 28/61] target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector)

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/translate-sme.c | 29 + target/arm/tcg/sme.decode | 15 +++ 3 files changed, 46 insertions(+) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translat

[PATCH 07/61] tcg: Split out tcg_gen_gvec_mov_var

Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec-common.h | 4 tcg/tcg-op-gvec.c| 21 +++-- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h index 6e8fccad01..cabbe

[PATCH 00/61] target/arm: Implement FEAT_SME2

Based-on: 20250201164012.1660228-1-peter.mayd...@linaro.org ("[PATCH v2 00/69] target/arm: FEAT_AFP and FEAT_RPRES") This implements the Scalar Matrix Extensions, version 2, plus two trivial extensions for float16 and bfloat16. This hasn't been tested much at all; I need to either get FVP up and

[PATCH 20/61] target/arm: Implement SME2 MOVA to/from tile, multiple registers

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 9 + target/arm/tcg/sme_helper.c| 64 ++ target/arm/tcg/translate-sme.c | 56 + target/arm/tcg/sme.decode | 37 4 files changed, 166

[PATCH 26/61] target/arm: Implement SME2 Multiple and Single SVE Destructive

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 13 target/arm/tcg/vec_internal.h | 4 ++ target/arm/tcg/helper-a64.c| 2 + target/arm/tcg/translate-sme.c | 115 + target/arm/tcg/vec_helper.c| 7 ++ target/arm/tcg/sme.deco

[PATCH 03/61] tcg: Add dbase argument to expand_clr

Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 451091753d..c26cfb24cc 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -380,7 +38

[PATCH 17/61] target/arm: Implement SME2 MOVT

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 13 + target/arm/tcg/sme.decode | 5 + 2 files changed, 18 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 8b0a33e2ae..13314c5cd7 100644 --- a/target/arm/t

[PATCH 09/61] target/arm: Introduce FPST_ZA, FPST_ZA_F16

Rather than repeatedly copying FPST_FPCR to locals and setting default nan mode, create dedicated float_status. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 12 +++- target/arm/cpu.c| 4 target/arm/vfp_helper.c | 10 ++ 3 files changed, 25 insertio

[PATCH 36/61] target/arm: Remove helper_gvec_sudot_idx_4b

Add gen_helper_gvec_sudot_idx_4b as an expander which swaps arguments and uses helper_gvec_usdot_idx_4b. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/translate.h | 3 +++ target/arm/tcg/gengvec.c| 6 ++ target/arm/tcg/vec_helper.c | 1 - 4 file

[PATCH 31/61] target/arm: Implement SME2 FMLAL, BFMLAL

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 93 ++ target/arm/tcg/sme.decode | 71 ++ 2 files changed, 164 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 8aae7

[PATCH 05/61] tcg: Split out tcg_gen_gvec_2_var

Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec-common.h | 3 ++ tcg/tcg-op-gvec.c| 85 2 files changed, 56 insertions(+), 32 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h index 65553f5

[PATCH 12/61] target/arm: Add isar_feature_aa64_sme2*

Signed-off-by: Richard Henderson --- target/arm/cpu-features.h | 35 +++ 1 file changed, 35 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 525e4cee12..5383d6b2d7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-fe

[PATCH 21/61] target/arm: Split out get_zarray

Prepare for MOVA array to/from vector with multiple registers by adding a div_len parameter, herein always 1. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 40 ++ 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/target/arm/tc

Re: [PATCH 2/6] hw/openrisc: Support monitor dumpdtb command

On 2/6/25 07:12, Peter Maydell wrote: The openrisc machines don't setMachineState::fdt to point to their DTB blob. This means that although the command line '-machine dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor commands do not, but instead produce the error "This machine d

Re: [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header

On 2/6/25 10:18, Philippe Mathieu-Daudé wrote: opentitan_machine_init() calls get_system_memory(), which is declared in "exec/address-spaces.h". Include it in order to avoid when refactoring unrelated headers: hw/riscv/opentitan.c:83:29: error: call to undeclared function 'get_system_memory'

Re: [PATCH 1/6] monitor/hmp-cmds.c: Clean up hmp_dumpdtb printf

On 2/6/25 07:12, Peter Maydell wrote: In hmp_dumpdtb(), we print a message when the command succeeds. This message is missing the trailing \n, so the HMP command prompt is printed immediately after it. We also weren't capitalizing 'DTB', or quoting the filename in the message. Fix these nits.

Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3

On Thu, Feb 06, 2025 at 04:38:55PM -0400, Jason Gunthorpe wrote: > On Thu, Feb 06, 2025 at 12:33:19PM -0800, Nicolin Chen wrote: > > On Thu, Feb 06, 2025 at 02:22:01PM -0400, Jason Gunthorpe wrote: > > > On Thu, Feb 06, 2025 at 06:18:14PM +, Shameerali Kolothum Thodi wrote: > > > > > > > > So

Re: [PATCH 5/6] hw: Centralize handling of -machine dumpdtb option

On 2/6/25 07:12, Peter Maydell wrote: Currently we handle the 'dumpdtb' machine sub-option ad-hoc in every board model that has an FDT. It's up to the board code to make sure it calls qemu_fdt_dumpdtb() in the right place. This means we're inconsistent and often just ignore the user's command l

Re: [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address

On 2/6/25 10:18, Philippe Mathieu-Daudé wrote: -M: Alistair Francis +M: alistair.francis Well this isn't right. r~

Re: [PATCH 6/6] hw/core/machine.c: Make -machine dumpdtb=file.dtb with no DTB an error

On 2/6/25 07:12, Peter Maydell wrote: Currently if the user requests via -machine dumpdtb=file.dtb that we dump the DTB, but the machine doesn't have a DTB, we silently ignore the option. This is confusing to users, and is a legacy of the old board-specific implementation of the option, where if

Re: [RFC PATCH 0/4] crypto,io,migration: Add support to gnutls_bye()

On 6.02.2025 18:58, Fabiano Rosas wrote: Hi, We've been discussing a way to stop multifd recv threads from getting an error at the end of migration when the source threads close the iochannel without ending the TLS session. The original issue was introduced by commit 1d457daf86 ("migration/mult

Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3

On Thu, Feb 06, 2025 at 12:48:40PM -0800, Nicolin Chen wrote: > On Thu, Feb 06, 2025 at 04:38:55PM -0400, Jason Gunthorpe wrote: > > On Thu, Feb 06, 2025 at 12:33:19PM -0800, Nicolin Chen wrote: > > > On Thu, Feb 06, 2025 at 02:22:01PM -0400, Jason Gunthorpe wrote: > > > > On Thu, Feb 06, 2025 at 0

[PATCH 30/61] target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s

Indicate whether to use FPST_FPCR or FPST_ZA via bit 2 of simd_data(desc). For SVE, this bit remains zero. For do_FMLAL_zzzw, this requires no change. For do_FMLAL_zzxw, move the index up one bit. Read fz16 directly from env->fpcr. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-

[PATCH 48/61] target/arm: Implement SME2 FCVTZS, FCVTZU

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 5 + target/arm/tcg/sme.decode | 9 + 2 files changed, 14 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 2b45244e23..4b45459e77 100644 --- a/target/arm/tcg/tra

[PATCH 15/61] target/arm: Implement SME2 ZERO ZT0

Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 1 + target/arm/tcg/translate-sme.c | 26 ++ target/arm/tcg/sme.decode | 1 + 3 files changed, 28 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 3244e0740d..c48d3b

[PATCH 34/61] target/arm: Implement SME2 FVDOT, BFVDOT

Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 ++ target/arm/tcg/helper-sme.h| 2 ++ target/arm/tcg/sme_helper.c| 30 ++ target/arm/tcg/translate-sme.c | 16 ++ target/arm/tcg/vec_helper.c| 39

[PATCH 19/61] target/arm: Rename MOVA for translate

Prepare for more kinds of MOVA from SME2 by renaming the existing SME1 MOVA to indicate tile to/from vector. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 12 +- target/arm/tcg/sme.decode | 42 +- 2 files changed, 27 insertions

[PATCH 33/61] target/arm: Implement SME2 BFDOT

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 17 + target/arm/tcg/sme.decode | 9 + 2 files changed, 26 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 2885655cc5..c03daa535d 100644 --- a/targ

[PATCH 27/61] target/arm: Implement SME2 Multiple Vectors SVE Destructive

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 65 ++ target/arm/tcg/sme.decode | 36 +++ 2 files changed, 101 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 0e05153924..

[PATCH 24/61] target/arm: Implement SME2 SMOPS, UMOPS (2-way)

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 4 target/arm/tcg/sme_helper.c| 37 +- target/arm/tcg/translate-sme.c | 2 ++ target/arm/tcg/sme.decode | 2 ++ 4 files changed, 35 insertions(+), 10 deletions(-) diff --git a/t

[PATCH 39/61] target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 29 ++ target/arm/tcg/sme.decode | 44 ++ 2 files changed, 73 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 492933d42d

[PATCH 14/61] target/arm: Add zt0_excp_el to DisasContext

Pipe the value through from SMCR_ELx through hflags and into the disassembly context. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/tcg/translate.h | 1 + target/arm/cpu.c | 3 +++ target/arm/tcg/hflags.c| 34 +

[PATCH 60/61] target/arm: Implement SME2 SEL

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 25 + target/arm/tcg/sme.decode | 9 + 2 files changed, 34 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e71e3ec8e3..78bd750701 100644 --

[PATCH 29/61] target/arm: Implement SME2 ADD/SUB (array results, multiple vectors)

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 31 +++ target/arm/tcg/sme.decode | 20 2 files changed, 51 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 09a4da1725..8aa

[PATCH 44/61] target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB

Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 ++ target/arm/tcg/translate-sme.c | 44 ++ target/arm/tcg/vec_helper.c| 2 ++ target/arm/tcg/sme.decode | 25 +++ 4 files changed, 73 insertions(+) diff --git a/tar

[PATCH 11/61] target/arm: Rename zarray to za_state.za

The whole ZA state will also contain ZT0. Make things easier in aarch64_set_svcr to zero both by wrapping them in a common structure. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 48 +++--- linux-user/aarch64/signal.c| 4 +-- target/arm/c

[PATCH 45/61] target/arm: Remove CPUARMState.vfp.scratch

The last use of this field was removed in b2fc7be972b9. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 61f959af8b..91edeae9ad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -693,9 +693

[PATCH 58/61] target/arm: Implement SME2 ZIP, UZP (two registers)

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 12 +++ target/arm/tcg/sme_helper.c| 58 ++ target/arm/tcg/translate-sme.c | 37 ++ target/arm/tcg/sme.decode | 12 +++ 4 files changed, 119 insertions(+) di

[PATCH 49/61] target/arm: Implement SME2 SCVTF, UCVTF

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 5 + target/arm/tcg/sme.decode | 5 + 2 files changed, 10 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 4b45459e77..a993870812 100644 --- a/target/arm/tcg/transla

[PATCH 18/61] target/arm: Split get_tile_rowcol argument tile_index

Decode tile number and index offset beforehand and separately. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 17 + target/arm/tcg/sme.decode | 46 +++--- 2 files changed, 38 insertions(+), 25 deletions(-) diff --git a/target/a

[PATCH 32/61] target/arm: Implement SME2 FDOT

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 5 target/arm/tcg/sme_helper.c| 44 ++ target/arm/tcg/translate-sme.c | 18 ++ target/arm/tcg/sme.decode | 14 +++ 4 files changed, 81 insertions(+) diff --git

[PATCH 23/61] target/arm: Implement SME2 BMOPA

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 3 +++ target/arm/tcg/sme_helper.c| 34 -- target/arm/tcg/translate-sme.c | 2 ++ target/arm/tcg/sme.decode | 2 ++ 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/ta

[PATCH 02/61] tcg: Add dbase argument to do_dup

Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 1aad7b0864..451091753d 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -534,9 +534,9 @@

[PATCH 22/61] target/arm: Implement SME2 MOVA to/from array, multiple registers

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 5 + target/arm/tcg/translate-sme.c | 30 ++ target/arm/tcg/sme.decode | 12 3 files changed, 47 insertions(+) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/transla

[PATCH 41/61] target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix

Emphasize the non-fused nature of these multiply-add. Matches other helpers such as gvec_rsqrts_nf_[hs]. Signed-off-by: Richard Henderson --- target/arm/helper.h | 8 target/arm/tcg/translate-neon.c | 4 ++-- target/arm/tcg/vec_helper.c | 8 3 files changed, 10

[PATCH 59/61] target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 15 + target/arm/tcg/sme_helper.c| 52 +++ target/arm/tcg/translate-sme.c | 56 ++ target/arm/tcg/sme.decode | 17 +++ 4 files changed, 140 in

[PATCH 38/61] target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 11 + target/arm/tcg/sme_helper.c| 42 ++ target/arm/tcg/translate-sme.c | 23 +++ target/arm/tcg/sme.decode | 11 + 4 files changed, 87 insertions(+) di

[PATCH 50/61] target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 9 + target/arm/tcg/sme.decode | 9 + 2 files changed, 18 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index a993870812..a4c683e12f 100644 --- a/target/arm/tcg

[PATCH 40/61] target/arm: Implement SME2 SMLALL, SMLSLL, UMLALL, UMLSLL

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 22 ++ target/arm/tcg/sme_helper.c| 60 +++ target/arm/tcg/translate-sme.c | 78 +++ target/arm/tcg/sme.decode | 135 + 4 files changed, 295 insertions

[PATCH 42/61] target/arm: Implement SME2 FMLA, FMLS

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 95 ++ target/arm/tcg/sme.decode | 48 + 2 files changed, 143 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 9c0989baff..19

[PATCH 53/61] target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 18 +++ target/arm/tcg/sme_helper.c| 91 ++ target/arm/tcg/translate-sme.c | 35 + target/arm/tcg/sme.decode | 22 4 files changed, 166 insertions(+) diff --git

[PATCH 61/61] target/arm: Enable FEAT_SME2, FEAT_SME_F16F16, FEAT_SVE_B16B16 on -cpu max

Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c| 7 ++- docs/system/arm/emulation.rst | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 29ab0ac79d..6fb821ad9a 100644 --- a/target/arm/tcg/cpu64.c +++

[PATCH 56/61] target/arm: Move do_urshr, do_srshr to vec_internal.h

Unify two copies of these inline functions. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 21 + target/arm/tcg/mve_helper.c | 21 - target/arm/tcg/sve_helper.c | 21 - 3 files changed, 21 insertions(+), 42 del

[PATCH 46/61] target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 5 +++ target/arm/tcg/sme_helper.c| 74 ++ target/arm/tcg/translate-sme.c | 25 target/arm/tcg/sme.decode | 12 ++ 4 files changed, 116 insertions(+) diff --git a/targ

[PATCH 25/61] target/arm: Introduce gen_gvec_sve2_sqdmulh

To be used by both SVE2 and SME2. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 4 target/arm/tcg/gengvec64.c | 11 +++ target/arm/tcg/translate-sve.c | 8 +--- 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/translate

[PATCH 01/61] tcg: Add dbase argument to do_dup_store

Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index d32a4f146d..1aad7b0864 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -483,8 +483,8 @@ static TCGType

[PATCH 51/61] target/arm: Introduce do_[us]sat_[bhs] macros

Inputs are a wider type of indeterminate sign. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 205f85b8d3..ad6fef03e6 100644 --- a/target/arm/tcg/vec_

[PATCH 43/61] target/arm: Implement SME2 BFMLA, BFMLS

Signed-off-by: Richard Henderson --- target/arm/helper.h| 9 + target/arm/tcg/translate-sme.c | 14 ++ target/arm/tcg/vec_helper.c| 26 ++ target/arm/tcg/sme.decode | 18 ++ 4 files changed, 67 insertions(+) diff -

[PATCH 47/61] target/arm: Implement SME2 FCVT (widening), FCVTL

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 2 ++ target/arm/tcg/sme_helper.c| 38 ++ target/arm/tcg/translate-sme.c | 5 + target/arm/tcg/sme.decode | 5 + 4 files changed, 50 insertions(+) diff --git a/target/arm/tcg

[PATCH 52/61] target/arm: Use do_[us]sat_[bhs] in sve_helper.c

Replace and remove do_sat_bhs. This avoids multiple repetitions of INT*_MIN/MAX. Signed-off-by: Richard Henderson --- target/arm/tcg/sve_helper.c | 116 +++- 1 file changed, 48 insertions(+), 68 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/t

[PATCH 54/61] target/arm: Implement SME2 SUNPK, UUNPK

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 13 target/arm/tcg/sme_helper.c| 38 ++ target/arm/tcg/translate-sme.c | 16 ++ target/arm/tcg/sme.decode | 18 4 files changed, 85 insertions(+

[PATCH 37/61] target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT

Signed-off-by: Richard Henderson --- target/arm/helper.h| 6 +++ target/arm/tcg/translate-sme.c | 85 ++ target/arm/tcg/vec_helper.c| 51 target/arm/tcg/sme.decode | 63 - 4 files changed, 204 inser

[PATCH 57/61] target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 18 +++ target/arm/tcg/sme_helper.c| 94 ++ target/arm/tcg/translate-sme.c | 29 +++ target/arm/tcg/sme.decode | 33 4 files changed, 174 insertions(+) diff --g

[PATCH 55/61] target/arm: Implement SME2 ZIP, UZP (four registers)

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h| 12 ++ target/arm/tcg/sme_helper.c| 68 ++ target/arm/tcg/translate-sme.c | 35 + target/arm/tcg/sme.decode | 11 ++ 4 files changed, 126 insertions(+) diff --gi

Re: [PATCH 2/7] guest_memfd: Introduce an object to manage the guest-memfd with RamDiscardManager

On Thu, Feb 06, 2025 at 06:41:09PM +0800, Xu Yilun wrote: > On Thu, Jan 30, 2025 at 11:28:11AM -0500, Peter Xu wrote: > > On Sun, Jan 26, 2025 at 11:34:29AM +0800, Xu Yilun wrote: > > > > Definitely not suggesting to install an invalid pointer anywhere. The > > > > mapped pointer will still be val

[PATCH 35/61] target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh]

Emphasize that these are 4-way dot products. Signed-off-by: Richard Henderson --- target/arm/helper.h | 22 +++--- target/arm/tcg/translate-a64.c | 14 +++--- target/arm/tcg/translate-neon.c | 14 +++--- target/arm/tcg/translate-sve.c | 18 +-

Re: [PULL 0/7] 9p queue 2025-02-06

; of https://gitlab.com/marcandre.lureau/qemu > > into staging (2025-02-03 13:42:02 -0500) > > > > are available in the Git repository at: > > > > https://github.com/cschoenebeck/qemu.git tags/pull-9p-20250206 > > > > for you to fetch changes up to bfa7bf0

[PATCH v5 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

Following changes are implemented in this series. 1. Fixed the cache(L2,L3) property details in all the EPYC models. 2. Add RAS feature bits (SUCCOR, McaOverflowRecov) on all EPYC models 3. Add missing SVM feature bits required for nested guests on all EPYC models 4. Add the missing feature bit

[PATCH v1 1/1] xen: No need to flush the mapcache for grants

From: Stefano Stabellini On IOREQ_TYPE_INVALIDATE we need to invalidate the mapcache for regular mappings. Since recently we started reusing the mapcache also to keep track of grants mappings. However, there is no need to remove grant mappings on IOREQ_TYPE_INVALIDATE requests, we shouldn't do th

[PATCH v1 0/1] xen: Remove invalidation of mapcache_grants on IOREQ_TYPE_INVALIDATE

From: "Edgar E. Iglesias" Olaf reported a slowdown in boot time on x86 HVM guests and Stefano provided a patch that removes the invalidation of the grants mapcache since not needed, more details here: https://lore.kernel.org/all/Z5oIvUINVDfrrVla@zapote/T/ Cheers, Edgar Stefano Stabellini (1):

[PATCH 08/61] tcg: Split out tcg_gen_gvec_{add,sub}_var

Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec-common.h | 9 + tcg/tcg-op-gvec.c| 32 ++-- 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h index c

[PATCH 04/61] tcg: Add base arguments to check_overlap_[234]

Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 55 ++- 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index c26cfb24cc..54304d08cc 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@

[PATCH 10/61] target/arm: Use FPST_ZA for sme_fmopa_[hsd]

Signed-off-by: Richard Henderson --- target/arm/tcg/sme_helper.c| 37 -- target/arm/tcg/translate-sme.c | 4 ++-- 2 files changed, 10 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index dcc48e43db..d4562

[PATCH 16/61] target/arm: Implement SME2 LDR/STR ZT0

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sme.c | 12 target/arm/tcg/sme.decode | 6 ++ 2 files changed, 18 insertions(+) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 37f4d341f0..8b0a33e2ae 100644 --- a/target/arm/t

Re: [PATCH 02/22] target/riscv: introduce RISCVCPUDef

On 2/6/25 10:26, Paolo Bonzini wrote: Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. ... diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ed9da692030..29cfae38b

Re: [PATCH 3/4] vfio/igd: use PCI ID defines to detect IGD gen

On Thu, 6 Feb 2025 13:13:39 +0100 Corvin Köhne wrote: > From: Corvin Köhne > > We've recently imported the PCI ID list of knwon Intel GPU devices from > Linux. It allows us to properly match GPUs to their generation without > maintaining an own list of PCI IDs. > > Signed-off-by: Corvin Köhne

Re: [PATCH v5 02/16] hw/net/xilinx_ethlite: Make device endianness configurable

On 2/6/25 05:10, Philippe Mathieu-Daudé wrote: Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine usi

Re: [PATCH v4 15/16] tests/functional: Move microblaze tests to common parent class

On 06/02/2025 12.33, Philippe Mathieu-Daudé wrote: Move the xmaton and ballerina tests to the parent class. Signed-off-by: Philippe Mathieu-Daudé --- .../functional/test_microblaze_s3adsp1800.py | 27 +-- .../test_microblazeel_s3adsp1800.py | 26 +-

[PATCH v5 00/16] hw/microblaze: Allow running cross-endian vCPUs

Missing review: 2 & 14 (new) Since v4 & v3: - Addressed Thomas review comments Since v2: - Addressed Richard's review comments Since v1: - Make device endianness configurable (Edgar) - Convert more Xilinx devices - Avoid preprocessor #if (Richard) - Add R-b tags Make machines endianness-agnosti

Re: [PATCH v4 2/4] qdev-properties: Accept bool for OnOffAuto

On Thu, 6 Feb 2025, Akihiko Odaki wrote: On 2025/02/06 18:48, Markus Armbruster wrote: This problem can be solved using an existing mechanism, OnOffAuto, which differentiates the "auto" state and explicit the "on" state. I guess you're proposing som

Re: Call for GSoC internship project ideas

On Thu, Feb 6, 2025 at 4:34 AM Matias Ezequiel Vara Larsen wrote: > === Adding Kani proofs for Virtqueues in Rust-vmm === > > '''Summary:''' Verify conformance of the virtqueue implementation in > rust-vmm to the VirtIO specification. > > In the rust-vmm project, devices rely on the virtqueue impl

Re: [PATCH v4 08/33] migration/multifd: Allow premature EOF on TLS incoming channels

"Maciej S. Szmigiero" writes: > On 6.02.2025 16:20, Fabiano Rosas wrote: >> "Maciej S. Szmigiero" writes: >> >>> On 6.02.2025 15:13, Fabiano Rosas wrote: "Maciej S. Szmigiero" writes: > On 5.02.2025 21:42, Fabiano Rosas wrote: >> Fabiano Rosas writes: >> >>> Daniel P

Re: [PATCH v2 15/18] hw/arm/fsl-imx8mp: Add USB support

On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote: > > Split the USB MMIO regions to better keep track of the implemented vs. > unimplemented regions. > > Signed-off-by: Bernhard Beschow > --- > docs/system/arm/imx8mp-evk.rst | 1 + > include/hw/arm/fsl-imx8mp.h| 12 +++ > hw/arm/

Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines

On Thu, Feb 6, 2025 at 7:04 AM Philippe Mathieu-Daudé wrote: > On 6/2/25 15:31, Daniel P. Berrangé wrote: > > We would pick an arbitrary endianness of our choosing > > I guess. How does this work in physical machines ? Is > > the choice of endianess a firmware setting, or a choice > > by the vendo

Re: [PATCH v2 17/18] hw/arm/fsl-imx8mp: Add on-chip RAM

On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote: > > Signed-off-by: Bernhard Beschow > --- > include/hw/arm/fsl-imx8mp.h | 1 + > hw/arm/fsl-imx8mp.c | 11 +++ > 2 files changed, 12 insertions(+) > Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 18/18] hw/rtc: Add Ricoh RS5C372 RTC emulation

On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote: > > The implementation just allows Linux to determine date and time. > > Signed-off-by: Bernhard Beschow > --- > MAINTAINERS | 1 + > hw/rtc/rs5c372.c| 227 > hw/rtc/Kconfig | 5

[PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

We only support 32-bit TriCore architecture. Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6819b776686..c5b783b6a70 100644 --- a/target/tri

Re: [PATCH v2 07/18] hw/arm/fsl-imx8mp: Add USDHC storage controllers

On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote: > > The USDHC emulation allows for running real-world images such as those > generated > by Buildroot. Convert the board documentation accordingly instead of running a > Linux kernel with ephemeral storage. > > Signed-off-by: Bernhard Beschow

Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines

On 6/2/25 18:34, Max Filippov wrote: On Thu, Feb 6, 2025 at 7:04 AM Philippe Mathieu-Daudé wrote: On 6/2/25 15:31, Daniel P. Berrangé wrote: We would pick an arbitrary endianness of our choosing I guess. How does this work in physical machines ? Is the choice of endianess a firmware setting, o

Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3

On Thu, Feb 06, 2025 at 05:10:32PM +, Daniel P. Berrangé wrote: > On Thu, Feb 06, 2025 at 01:02:38PM -0400, Jason Gunthorpe wrote: > > On Thu, Feb 06, 2025 at 03:07:06PM +, Shameerali Kolothum Thodi wrote: > > > > If we set the physical/guest SMMU relationship directly, then at the > > > >

Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

On 2/6/25 09:32, Philippe Mathieu-Daudé wrote: We only support 32-bit TriCore architecture. Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c ind

Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines

On 6/2/25 18:12, Daniel P. Berrangé wrote: On Thu, Feb 06, 2025 at 04:04:20PM +0100, Philippe Mathieu-Daudé wrote: On 6/2/25 15:31, Daniel P. Berrangé wrote: On Thu, Feb 06, 2025 at 02:53:58PM +0100, Philippe Mathieu-Daudé wrote: Hi Daniel, On 6/2/25 14:20, Daniel P. Berrangé wrote: On Thu,

Re: [PATCH] hw/sd/sdhci: Set reset value of interrupt registers

On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote: On 15/1/25 20:04, BALATON Zoltan wrote: The interrupt enable registers are not reset to 0 but some bits are enabled on reset. At least some U-Boot versions seem to expect this and not initialise these registers before expecting interrupts. The nu

Re: [PATCH v2 4/8] hw/boards: Remove all invalid uses of auto_create_sdcard=true

On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote: On 5/2/25 08:03, Markus Armbruster wrote: Philippe Mathieu-Daudé writes: MachineClass::auto_create_sdcard is only useful to automatically create a SD card, attach a IF_SD block drive to it and plug the card onto a SD bus. Only the ARM and RISC

Re: [PATCH v4 14/16] tests/functional: Have microblaze tests inherit common parent class

On 06/02/2025 12.33, Philippe Mathieu-Daudé wrote: Have the MicroblazeMachine class being common to both MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine classes. Signed-off-by: Philippe Mathieu-Daudé --- tests/functional/test_microblaze_s3adsp1800.py | 2 ++ tests/functional/t

[PATCH v5 04/16] hw/char/xilinx_uartlite: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Reviewed-by: Richard Henderson S

[PATCH v5 07/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philip

[PATCH v5 01/16] hw/intc/xilinx_intc: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Reviewed-by: Richard Henderson Signed

Re: [PATCH V1 12/26] vfio-pci: preserve MSI

On 2/5/2025 11:48 AM, Cédric Le Goater wrote: On 1/29/25 15:43, Steve Sistare wrote: Save the MSI message area as part of vfio-pci vmstate, and preserve the interrupt and notifier eventfd's.  migrate_incoming loads the MSI data, then the vfio-pci post_load handler finds the eventfds in CPR state

Re: [RFC v2 3/5] i386/kvm: Support event with select & umask format in KVM PMU filter

> > Do users need to know how to compute the raw event value from @select > > and @umask? > > Yes, because it's also a unified calculation. AMD and Intel have > differences in bits for supported select field, but this calculation > (which follows from the KVM code) makes both compatible. > > > If

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