Hi,
> > Is there some simple way to figure what the iommu width is (inside the
> > guest)?
>
> If the guest firmware is exposing a DMAR table (VT-d), there's a host
> address width field in that table. Otherwise there are capability
> registers on the DRHD units that could be queried. AMD-Vi
On 17/1/25 20:40, Paolo Bonzini wrote:
In practice it has to be implemented always in order to access an
implementation of ClassInitImpl. Make the relationship
explicit in the code.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/qdev.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Hi Hao,
On 6/2/25 02:30, Hao Wu wrote:
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 131 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 134 insertions(+), 3 deletions(-)
+NPCM8XX_GCR_WD0RCRBLK,
+N
On 2/6/25 10:15, Zhao Liu wrote:
Throughout the entire holiday, I couldn't think of a better way to
express this. I find it particularly useful when wrapping multiple
callbacks. In the future, I want to explore more use cases where this
pattern can be applied.
Thanks very much. Despite having
Not a major change but, as a small but significant step in creating
qdev bindings, show how pl011_create can be written without "unsafe"
calls (apart from converting pointers to references).
This also provides a starting point for creating Error** bindings.
Signed-off-by: Paolo Bonzini
---
rust
Without it, recent bindgen will give an error
error: extern block cannot be declared unsafe
if rustc is not new enough to support the "unsafe extern" construct.
Cc: qemu-r...@nongnu.org
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
meson.build | 3 +++
1 file changed, 3 insert
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Reviewed-by: Richard Henderson
Signed
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/microblaze); \
done
Signed-off-by: Philip
All callers of do_load() / do_store() set MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/translate.c | 36 +++
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/targ
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Reviewed-by: Richard Henderson
S
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Reviewed-by: Richard Henderson
Signed
Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/cpu.h | 7 +++
target/microblaze/translate.c | 5 +++--
2 files changed, 10 insertions(+), 2 de
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Reviewed-by: Richard Henderson
S
Ensure microblaze machines can run cross-endianness by
running all tests on all machines.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblaze_s3adsp1800.py | 6 ++
tests/functional/test_microblazeel_s3adsp1800.py | 6 ++
2 files changed, 12 insertions(+)
diff --
Have the MicroblazeMachine class being common to both
MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine
classes.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblaze_s3adsp1800.py | 2 ++
tests/functional/test_microblazeel_s3adsp1800.py | 5 ++---
2 files chang
Move the xmaton and ballerina tests to the parent class.
Signed-off-by: Philippe Mathieu-Daudé
---
.../functional/test_microblaze_s3adsp1800.py | 27 +--
.../test_microblazeel_s3adsp1800.py | 26 +-
2 files changed, 26 insertions(+), 27 deletions(-)
di
When a property value is static (not provided by QMP or CLI),
error shouldn't happen, otherwise it is a programming error.
Therefore simplify and use &error_abort as this can't fail.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
---
hw/arm/xl
Make microblaze tests a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblaze_s3adsp1800.py | 7 +--
tests/functional/test_microblazeel_s3adsp1800.py | 7 +--
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_mi
Introduce an abstract machine parent class which defines
the 'little_endian' property. Duplicate the current machine,
which endian is tied to the binary endianness, to one big
endian and a little endian machine; updating the machine
description. Keep the current default machine for each binary.
'p
On Thu, Feb 6, 2025 at 12:37 PM Philippe Mathieu-Daudé
wrote:
> > if bindgen.version().version_compare('<0.61.0')
> > # default in 0.61+
> > bindgen_args += ['--size_t-is-usize']
>
> Should this be merged directly on master as build-fix?
If it's breaking CI I can send a pull reque
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-D
The archive used in test_microblaze_s3adsp1800.py (testing a
big-endian target) contains a big-endian kernel. Rename using
the _BE suffix.
Similarly, the archive in test_microblazeel_s3adsp1800 (testing
a little-endian target) contains a little-endian kernel. Rename
using _LE suffix.
These change
On 5.02.2025 16:55, Peter Xu wrote:
On Wed, Feb 05, 2025 at 12:53:21PM +0100, Maciej S. Szmigiero wrote:
On 4.02.2025 21:34, Peter Xu wrote:
On Tue, Feb 04, 2025 at 08:32:15PM +0100, Maciej S. Szmigiero wrote:
On 4.02.2025 18:54, Peter Xu wrote:
On Thu, Jan 30, 2025 at 11:08:40AM +0100, Macie
On 6/2/25 10:58, Paolo Bonzini wrote:
Currently, the instance_post_init calls are performed from the leaf
class and all the way up to Object. This is incorrect because the
leaf class cannot observe property values applied by the superclasses;
for example, a compat property will be set on a devic
On 6/2/25 12:38, Paolo Bonzini wrote:
On Thu, Feb 6, 2025 at 12:37 PM Philippe Mathieu-Daudé
wrote:
if bindgen.version().version_compare('<0.61.0')
# default in 0.61+
bindgen_args += ['--size_t-is-usize']
Should this be merged directly on master as build-fix?
If it's brea
On 6/2/25 12:15, Paolo Bonzini wrote:
Without it, recent bindgen will give an error
error: extern block cannot be declared unsafe
if rustc is not new enough to support the "unsafe extern" construct.
Cc: qemu-r...@nongnu.org
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
mes
On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis wrote:
>
> On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal wrote:
> >
> > This series enables Control Transfer Records extension support on riscv
> > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> > The Extension has been ra
On 24/01/25 03:19PM, Jonathan Cameron wrote:
On Thu, 23 Jan 2025 10:39:03 +0530
Vinayak Holikatti wrote:
CXL spec 3.1 section 8.2.9.9.5.3 describes media operations commands.
CXL devices supports media operations Sanitize and Write zero command.
As before, don't indent this.
Signe
On 03/02/25 05:02PM, Adam Manzanares wrote:
On Mon, Feb 03, 2025 at 11:33:54AM +, Jonathan Cameron wrote:
> >
> > > +int dpa_range_count = san_info->dpa_range_count;
> > > +int rc = 0;
> > > +
> > > +for (int i = 0; i < dpa_range_count; i++) {
> > > +rc = sanitize_range(
On Wed, Feb 05, 2025 at 11:07:10AM +0100, Markus Armbruster wrote:
> Date: Wed, 05 Feb 2025 11:07:10 +0100
> From: Markus Armbruster
> Subject: Re: [RFC v2 3/5] i386/kvm: Support event with select & umask
> format in KVM PMU filter
>
> Zhao Liu writes:
>
> > The select&umask is the common way
On 05/02/2025 19.25, Richard Henderson wrote:
On 2/5/25 08:53, Daniel P. Berrangé wrote:
+Decorator to skip execution of a test on 32-bit targets
+Example:
+
+ @skipIf32BitTarget()
+'''
+def skipIf32BitTarget():
+ enoughBits = sys.maxsize > 2**32
+ return skipUnless(enoughBits,
+
On Wed, Feb 05, 2025 at 10:24:08AM -0800, Richard Henderson wrote:
> On 2/5/25 07:59, Daniel P. Berrangé wrote:
> > +
> > +'''
> > +Decorator to skip execution of a test on 32-bit targets
> > +Example:
> > +
> > + @skipIf32BitTarget()
> > +'''
> > +def skipIf32BitTarget():
> > +enoughBits = sy
On 10/1/25 15:51, Zhao Liu wrote:
Currently, neither i386 nor ARM have real hardware support for per-
thread cache, and there is no clear demand for this specific cache
topology.
Additionally, since ARM even can't support this special cache topology
in device tree, it is unnecessary to support i
Daniel P. Berrangé writes:
> On Wed, Jan 08, 2025 at 03:17:51PM +0900, Akihiko Odaki wrote:
>> Accept bool literals for OnOffAuto properties for consistency with bool
>> properties. This enables users to set the "on" or "off" value in a
>> uniform syntax without knowing whether the "auto" value i
On Tue, Jan 28, 2025 at 11:16:43AM -0500, Stefan Hajnoczi wrote:
> Dear QEMU and KVM communities,
> QEMU will apply for the Google Summer of Code internship
> program again this year. Regular contributors can submit project
> ideas that they'd like to mentor by replying to this email by
> February
Cc'ing more developers.
On 4/2/25 22:44, Philippe Mathieu-Daudé wrote:
ping?
On 25/1/25 19:24, Philippe Mathieu-Daudé wrote:
Update few QEMUTimer docstring and add a
sanity check during timer initialization.
Noticed trying to understand leaks in QDev
Realize -> Unrealize -> Realize transition
On Fri, Jan 17, 2025 at 08:40:01PM +0100, Paolo Bonzini wrote:
> Date: Fri, 17 Jan 2025 20:40:01 +0100
> From: Paolo Bonzini
> Subject: [PATCH 08/10] rust: qdev: switch from legacy reset to Resettable
> X-Mailer: git-send-email 2.47.1
>
> Signed-off-by: Paolo Bonzini
> ---
> meson.build
Akihiko Odaki writes:
> On 2025/02/06 0:29, Markus Armbruster wrote:
>> Akihiko Odaki writes:
>>
>>> Accept bool literals for OnOffAuto properties for consistency with bool
>>> properties. This enables users to set the "on" or "off" value in a
>>> uniform syntax without knowing whether the "aut
On Thu, Feb 06, 2025 at 05:54:32PM +0800, Zhao Liu wrote:
> On Wed, Feb 05, 2025 at 11:07:10AM +0100, Markus Armbruster wrote:
> > Date: Wed, 05 Feb 2025 11:07:10 +0100
> > From: Markus Armbruster
> > Subject: Re: [RFC v2 3/5] i386/kvm: Support event with select & umask
> > format in KVM PMU filt
mo_endian() returns the target endianness, currently static.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/translate.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microbla
On 24/1/25 18:50, Philippe Mathieu-Daudé wrote:
- Parity in realize / unrealize
- Define TypeInfo structure
Philippe Mathieu-Daudé (2):
hw/char/sh_serial: Delete fifo_timeout_timer in DeviceUnrealize
hw/char/sh_serial: Convert to TypeInfo
hw/char/sh_serial.c | 24 ++-
On Wed, Jan 29, 2025 at 09:37:03AM +0100, Paolo Bonzini wrote:
> Date: Wed, 29 Jan 2025 09:37:03 +0100
> From: Paolo Bonzini
> Subject: [PATCH 1/2] rust: remove unnecessary Cargo.toml metadata
> X-Mailer: git-send-email 2.48.1
>
> Some items of Cargo.toml (readme, homepage, repository) are
> only
Zhao Liu writes:
> On Wed, Feb 05, 2025 at 11:03:51AM +0100, Markus Armbruster wrote:
>> Date: Wed, 05 Feb 2025 11:03:51 +0100
>> From: Markus Armbruster
>> Subject: Re: [RFC v2 1/5] qapi/qom: Introduce kvm-pmu-filter object
>>
>> Quick & superficial review for now.
>
> Thanks!
>
>> > diff --gi
From: Corvin Köhne
We're currently missing some GPU IDs already supported by the i915
kernel driver. Additionally, we've treated IvyBridge as gen 6 in the
past. According to i915 it's gen 7 [1]. It shouldn't cause any issues
yet because we treat gen 6 and gen 7 the same way. Nevertheless, we
shou
From: Corvin Köhne
Hi,
we're currently maintaining an own list of PCI IDs to match the generation of
Intels integrated graphic devices. Linux maintains a list too. It's list is
more recent, contains the full PCI ID of all devices and ships some macros to
easily match them. This patch series impo
From: Corvin Köhne
We've recently imported the PCI ID list of knwon Intel GPU devices from
Linux. It allows us to properly match GPUs to their generation without
maintaining an own list of PCI IDs.
Signed-off-by: Corvin Köhne
---
hw/vfio/igd.c | 77 -
From: Corvin Köhne
We've recently imported the PCI ID header for Intel GPUs into our tree.
Add it to our helper script to make it easier for us to sync this file
in the future.
Signed-off-by: Corvin Köhne
---
scripts/update-linux-headers.sh | 6 ++
1 file changed, 6 insertions(+)
diff --g
On Thu, Feb 06, 2025 at 05:18:56AM +, Suravee Suthikulpanit wrote:
> Add migration support for AMD IOMMU model by saving necessary AMDVIState
> parameters for MMIO registers, device table, command buffer, and event
> buffers.
>
> Signed-off-by: Suravee Suthikulpanit
> ---
> Changes from v1:
>
Hi Paolo,
A kindly ping. (I dropped the cache per thread; do you think this version
is ok?)
Thanks,
Zhao
On Fri, Jan 10, 2025 at 10:51:10PM +0800, Zhao Liu wrote:
> Date: Fri, 10 Jan 2025 22:51:10 +0800
> From: Zhao Liu
> Subject: [PATCH v7 RESEND 0/5] i386: Support SMP Cache Topology
> X-Maile
On 6/2/25 03:34, bibo mao wrote:
On 2025/2/5 下午8:06, Xianglai Li wrote:
When the KVM_REG_LOONGARCH_VCPU_RESET command word
is sent to the kernel through the kvm_set_one_reg interface,
the parameter source needs to be a legal address,
otherwise the kernel will return an error and the command word
On 05/02/2025 16.59, Daniel P. Berrangé wrote:
If QEMU_TEST_QEMU_BINARY is not set we currently assert in the setUp
function, resulting in a big traceback:
TAP version 13
Traceback (most recent call last):
File
"/var/home/berrange/src/virt/qemu/tests/functional/qemu_test/testca
Hi Hao,
On 6/2/25 02:30, Hao Wu wrote:
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 1
On 6/2/25 02:30, Hao Wu wrote:
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files
On 05/02/2025 16.59, Daniel P. Berrangé wrote:
This was copied over from avocado but has not been used in the new
functional tests.
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/testcase.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/fun
On 05/02/2025 16.59, Daniel P. Berrangé wrote:
The 'qemu_bin' field is currently set on the class, despite being
accessed as if it were an object instance field with 'self.qemu_bin'.
This is no obvious need to have it as a class field, so move it into
the object instance.
Signed-off-by: Daniel
On 6/2/25 02:31, Hao Wu wrote:
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not nec
On 05/02/2025 16.59, Daniel P. Berrangé wrote:
A number of fields are set at the class level on QemuBaseTest, even
though the exact same named field is then set at the object level
later in most cases.
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/testcase.py | 6 --
1
On 6/2/25 02:31, Hao Wu wrote:
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 253 +++
include/hw/arm/npcm8xx.h | 20
3 files changed, 274 insertions(+), 1 deletion(-)
create mod
On 2025/2/6 下午5:02, Philippe Mathieu-Daudé wrote:
On 6/2/25 03:34, bibo mao wrote:
On 2025/2/5 下午8:06, Xianglai Li wrote:
When the KVM_REG_LOONGARCH_VCPU_RESET command word
is sent to the kernel through the kvm_set_one_reg interface,
the parameter source needs to be a legal address,
otherwis
On 06/02/2025 10.35, Daniel P. Berrangé wrote:
On Wed, Feb 05, 2025 at 10:24:08AM -0800, Richard Henderson wrote:
On 2/5/25 07:59, Daniel P. Berrangé wrote:
+
+'''
+Decorator to skip execution of a test on 32-bit targets
+Example:
+
+ @skipIf32BitTarget()
+'''
+def skipIf32BitTarget():
+en
Hi Paolo,
On 17/1/25 20:40, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 43 +++---
rust/hw/char/pl011/src/lib.rs| 1 -
rust/hw/char/pl011/src/memory_ops.rs | 36 -
rust/qemu-api/meson.build| 1 +
rust/qemu-api/
On Thu, Feb 06, 2025 at 10:02:25AM +, Shameerali Kolothum Thodi wrote:
> Hi Daniel,
>
> > -Original Message-
> > From: Daniel P. Berrangé
> > Sent: Friday, January 31, 2025 9:42 PM
> > To: Shameerali Kolothum Thodi
> > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> > eric.au...@re
On Sat, Jan 25, 2025 at 07:24:24PM +0100, Philippe Mathieu-Daudé wrote:
> There was not mention QEMUTimer created with timer_new*() must
> be released with timer_free() instead of g_free(), because then
> active timers are removed from the active list. Update the
> documentation mentioning timer_fr
Hi Nicolin,
> -Original Message-
> From: Nicolin Chen
> Sent: Wednesday, February 5, 2025 12:09 AM
> To: Shameerali Kolothum Thodi
> ; Eric Auger
>
> Cc: ddut...@redhat.com; Peter Maydell ; Jason
> Gunthorpe ; Daniel P. Berrangé ;
> qemu-...@nongnu.org; qemu-devel@nongnu.org; Linuxarm
>
On Sat, Jan 25, 2025 at 07:24:25PM +0100, Philippe Mathieu-Daudé wrote:
> Ensure we are not re-initializing a QEMUTimer already added
> to an active list. timer_init*() functions expect either
> a recently created and zeroed QEMUTimer, or one previously
> free'd with timer_free().
>
> Signed-off-b
On Thu, Jan 30, 2025 at 11:28:11AM -0500, Peter Xu wrote:
> On Sun, Jan 26, 2025 at 11:34:29AM +0800, Xu Yilun wrote:
> > > Definitely not suggesting to install an invalid pointer anywhere. The
> > > mapped pointer will still be valid for gmem for example, but the fault
> > > isn't. We need to di
> diff --git a/rust/hw/char/pl011/src/device_class.rs
> b/rust/hw/char/pl011/src/device_class.rs
> index 8a157a663fb..dbef93f6cb3 100644
> --- a/rust/hw/char/pl011/src/device_class.rs
> +++ b/rust/hw/char/pl011/src/device_class.rs
> @@ -12,7 +12,6 @@
>
> use crate::device::{PL011Registers, PL01
On 5/2/25 08:03, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
MachineClass::auto_create_sdcard is only useful to automatically
create a SD card, attach a IF_SD block drive to it and plug the
card onto a SD bus. Only the ARM and RISCV targets use such
feature:
$ git grep -wl IF_SD
On 2025/02/06 18:48, Markus Armbruster wrote:
Akihiko Odaki writes:
On 2025/02/06 0:29, Markus Armbruster wrote:
Akihiko Odaki writes:
Accept bool literals for OnOffAuto properties for consistency with bool
properties. This enables users to set the "on" or "off" value in a
uniform syntax w
On 2/6/25 11:02, Philippe Mathieu-Daudé wrote:
Could we always make .valid_sizes() explicit?
Yes (for example build() could even fail to compile if you don't have
impl_sizes/valid_sizes set), but why do you want that? I'm not even
sure that all cases of .valid.max_access_size=4 are correct...
On 6/2/25 09:46, Paolo Bonzini wrote:
On Thu, Feb 6, 2025 at 9:40 AM Philippe Mathieu-Daudé wrote:
Hi Paolo,
On 17/1/25 20:40, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 43 +++---
rust/hw/char/pl011/src/lib.rs| 1 -
rust/h
Daniel P. Berrangé writes:
> On Thu, Feb 06, 2025 at 05:54:32PM +0800, Zhao Liu wrote:
>> On Wed, Feb 05, 2025 at 11:07:10AM +0100, Markus Armbruster wrote:
>> > Date: Wed, 05 Feb 2025 11:07:10 +0100
>> > From: Markus Armbruster
>> > Subject: Re: [RFC v2 3/5] i386/kvm: Support event with select
On Thu, Feb 6, 2025 at 9:40 AM Philippe Mathieu-Daudé wrote:
>
> Hi Paolo,
>
> On 17/1/25 20:40, Paolo Bonzini wrote:
> > Signed-off-by: Paolo Bonzini
> > ---
> > rust/hw/char/pl011/src/device.rs | 43 +++---
> > rust/hw/char/pl011/src/lib.rs| 1 -
> > rust/hw/char/pl011/src/me
On Fri, Jan 31, 2025 at 05:08:28PM +0100, Eric Auger wrote:
> Hi,
>
>
> On 1/31/25 4:23 PM, Shameerali Kolothum Thodi wrote:
> >
> >> -Original Message-
> >> From: Jason Gunthorpe
> >> Sent: Friday, January 31, 2025 2:54 PM
> >> To: Shameerali Kolothum Thodi
> >> Cc: Daniel P. Berrangé
On Wed, Feb 05, 2025 at 12:53:42PM -0800, Nathan Chen wrote:
>
>
> On 1/31/2025 8:08 AM, Eric Auger wrote:
> > > > > > > And Qemu does some checking to make sure that the device is indeed
> > > > > > associated
> > > > > > > with the specified phys-smmuv3. This can be done going through
> > > >
> > > +pub struct MemoryRegionOps(
> > > +bindings::MemoryRegionOps,
> > > +// Note: quite often you'll see PhantomData mentioned when
> > > discussing
> > > +// covariance and contravariance; you don't need any of those to
> > > understand
> > > +// this usage of PhantomData. Qu
On Wed, Feb 05, 2025 at 01:32:19PM +0100, Markus Armbruster wrote:
> Date: Wed, 05 Feb 2025 13:32:19 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH v7 RESEND 0/5] i386: Support SMP Cache Topology
>
> Zhao Liu writes:
>
> > Hi folks,
> >
> > This is my v7 resend version (updated the commi
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTC_IO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTC_IO. To make these trace events more readable, adds
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTC_IO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write b
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 39567fcab9..6a848
Here are two small fixes around mhpmevent encoding and reset value.
The first patch is picked from the platform specific event encoding
series[1].
[1]
https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e...@rivosinc.com/
Signed-off-by: Atish Patra
---
Changes in v2:
- Re
As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.
[1]https://github.com/riscv/riscv-isa-manual/issues/1578
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu_bi
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTC_IO (IO Die) model, introduces
Currently, the instance_post_init calls are performed from the leaf
class and all the way up to Object. This is incorrect because the
leaf class cannot observe property values applied by the superclasses;
for example, a compat property will be set on a device *after*
the class's post_init callback
As per the ISA definition, the upper 8 bits in hpmevent are defined
by Sscofpmf for privilege mode filtering and overflow bits while the
lower 56 bits are desginated for platform specific hpmevent values.
For the reset case, mhpmevent value should have zero in lower 56 bits.
Software may set the OF
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled on reset. At least some U-Boot versions seem to expect this
and not initialise these registers before expecting interrupts. The
numbers in this patch match what QorIQ P1022 has on r
On 6/2/25 02:31, Hao Wu wrote:
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 19 +--
include/hw/misc/npcm_clk.h
According to the AST2700 datasheet, the INTC (CPU DIE) controller has 16KB
(0x4000) of register space, and the INTC_IO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_...@aspeedtech.com/
This patch series focuses on cleaning up the INTC model to
facilitate future support for the I
On Wed, Feb 05, 2025 at 11:03:51AM +0100, Markus Armbruster wrote:
> Date: Wed, 05 Feb 2025 11:03:51 +0100
> From: Markus Armbruster
> Subject: Re: [RFC v2 1/5] qapi/qom: Introduce kvm-pmu-filter object
>
> Quick & superficial review for now.
Thanks!
> > diff --git a/qapi/kvm.json b/qapi/kvm.js
Hi Daniel,
> -Original Message-
> From: Daniel P. Berrangé
> Sent: Friday, January 31, 2025 9:42 PM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> nicol...@nvidia.com; ddut...@redhat.
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/
> > > > +##
> > > > +# @KVMPMUX86DefalutEventVariant:
>
> Typo s/Defalut/Default/ - repeated many times in this patch.
My bad! Will fix!
> > > > +#
> > > > +# The variant of KVMPMUX86DefalutEvent with the string, rather than
> > > > +# the numeric value.
> > > > +#
> > > > +# @select: x86 PMU
> > > @@ -1183,6 +1185,7 @@
> > >'if': 'CONFIG_LINUX' },
> > >'iommufd':'IOMMUFDProperties',
> > >'iothread': 'IothreadProperties',
> > > + 'kvm-pmu-filter': 'KVMPMUFilterPropertyVariant',
From: Corvin Köhne
Intels integrated graphics devices do require many quirks to pass them
to a VM as passthrough device. Unfortunately, those quirks are device
specific and we have to check the device IDs to apply quirks properly.
In the past, we've maintained an own list of PCI IDs. However, it'
On Thu, Feb 06, 2025 at 10:34:15AM +, Shameerali Kolothum Thodi wrote:
> > -Original Message-
> > From: Nicolin Chen
> > On Tue, Feb 04, 2025 at 06:49:15PM +0100, Eric Auger wrote:
> > > However in
> > >
> > > Shameer suggested he may include it in his SMMU multi instance series.
> > >
(sorry, posted too quick)
On 6/2/25 19:24, Philippe Mathieu-Daudé wrote:
+Michal
On 6/2/25 19:06, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 06:49:38PM +0100, Philippe Mathieu-Daudé wrote:
On 6/2/25 18:12, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 04:04:20PM +0100, Philippe Ma
;
> are available in the Git repository at:
>
> https://github.com/cschoenebeck/qemu.git tags/pull-9p-20250206
>
> for you to fetch changes up to bfa7bf02782dbd996201c90f850ca11730041af1:
>
> MAINTAINERS: Mark me as
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 4 ++
tcg/tcg-op-gvec.c| 102 +++
2 files changed, 68 insertions(+), 38 deletions(-)
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h
index 877871
This is a 512-bit array introduced with SME2.
Save it only when ZA is in use.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 +++
target/arm/machine.c | 21 +
2 files changed, 24 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 938c990854.
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