On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis <alistai...@gmail.com> wrote: > > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal <rkan...@rivosinc.com> wrote: > > > > This series enables Control Transfer Records extension support on riscv > > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. > > The Extension has been ratified and this series is based on v1.0 [0] > > > > CTR extension depends on both the implementation of S-mode and Sscsrind > > extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs > > using > > sscsrind extension. > > > > The series is based on Smcdeleg/Ssccfg counter delegation extension [2] > > patches [3]. CTR itself doesn't depend on counter delegation support. This > > rebase is basically to include the Smcsrind patches. > > > > Here is the link to a quick start guide [4] to setup and run a basic perf > > demo > > on Linux to use CTR Ext. > > > > Qemu patches can be found here: > > https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6 > > > > Opensbi patch can be found here: > > https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 > > > > Linux kernel patches can be found here: > > https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2 > > > > [0]: > > https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0 > > [1]: > > https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0 > > [2]: > > https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 > > [3]: > > https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89bae...@rivosinc.com/ > > [4]: > > https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine > > > > Signed-off-by: Rajnesh Kanwal <rkan...@rivosinc.com> > > --- > > Changelog: > > v6: Rebased on latest riscv-to-apply.for-upstream. > > It should be rebased on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > I applied the first 6 patches as they apply cleanly > > Alistair >
Sorry for the inconvenience. Strangely cherry-pick, patch and git am -3 all seem to work fine but git am seems to be failing. I looked into the conflict and it looks like am expects ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), but gets this in cpu.c. ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12), I have tried following cmds on top of riscv-to-apply.next and these fetch the last patch only and apply the last patch perfectly fine. b4 am -i -P="-1" 20250205-b4-ctr_upstream_v6-v6-0-439d8e06c...@rivosinc.com git am -3 ./v6_20250205_rkanwal_target_riscv_add_support_for_control_transfer_records_ext.mbx If you want I can send v7 as well rebased on top of riscv-to-apply.next. Thanks Rajnesh > > > > v5: Improvements based on Richard Henderson's feedback. > > - Fixed code gen logic to use gen_update_pc() instead of > > tcg_constant_tl(). > > - Some function renaming. > > - Rebased onto v4 of counter delegation series. > > - > > https://lore.kernel.org/qemu-riscv/20241205-b4-ctr_upstream_v3-v5-0-60b993aa5...@rivosinc.com/ > > > > v4: Improvements based on Richard Henderson's feedback. > > - Refactored CTR related code generation to move more code into > > translation side and avoid unnecessary code execution in generated > > code. > > - Added missing code in machine.c to migrate the new state. > > - > > https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9...@rivosinc.com > > > > v3: Improvements based on Jason Chien and Frank Chang's feedback. > > - Created single set of MACROs for CTR CSRs in cpu_bit.h > > - Some fixes in riscv_ctr_add_entry. > > - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range. > > - Improved extension dependency check. > > - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze. > > - Added implied rules for Smctr and Ssctr. > > - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops. > > - Some more cosmetic changes. > > - > > https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c482...@rivosinc.com/ > > > > v2: Lots of improvements based on Jason Chien's feedback including: > > - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz. > > - Fixed and added more CTR extension enable checks. > > - Fixed CTR CSR predicate functions. > > - Fixed external trap xTE bit checks. > > - One fix in freeze function for VS-mode. > > - Lots of minor code improvements. > > - Added checks in sctrclr instruction helper. > > - > > https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkan...@rivosinc.com/ > > > > v1: > > - > > https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkan...@rivosinc.com/ > > > > --- > > Rajnesh Kanwal (7): > > target/riscv: Remove obsolete sfence.vm instruction > > target/riscv: Add Control Transfer Records CSR definitions. > > target/riscv: Add support for Control Transfer Records extension CSRs. > > target/riscv: Add support to record CTR entries. > > target/riscv: Add CTR sctrclr instruction. > > target/riscv: machine: Add Control Transfer Record state description > > target/riscv: Add support to access ctrsource, ctrtarget, ctrdata > > regs. > > > > target/riscv/cpu.c | 26 ++- > > target/riscv/cpu.h | 13 ++ > > target/riscv/cpu_bits.h | 145 ++++++++++++ > > target/riscv/cpu_cfg.h | 2 + > > target/riscv/cpu_helper.c | 266 ++++++++++++++++++++++ > > target/riscv/csr.c | 294 > > ++++++++++++++++++++++++- > > target/riscv/helper.h | 2 + > > target/riscv/insn32.decode | 2 +- > > target/riscv/insn_trans/trans_privileged.c.inc | 18 +- > > target/riscv/insn_trans/trans_rvi.c.inc | 75 +++++++ > > target/riscv/insn_trans/trans_rvzce.c.inc | 21 ++ > > target/riscv/machine.c | 25 +++ > > target/riscv/op_helper.c | 48 ++++ > > target/riscv/tcg/tcg-cpu.c | 11 + > > target/riscv/translate.c | 46 ++++ > > 15 files changed, 986 insertions(+), 8 deletions(-) > > --- > > base-commit: 699291ba7774f1580584cd96f84ceda8cc4edb7e > > change-id: 20250205-b4-ctr_upstream_v6-71418cd245ee > > -- > > Best Regards, > > Rajnesh Kanwal > > > >
