Em Fri, 24 Jan 2025 13:30:54 +0100
Igor Mammedov escreveu:
> On Wed, 22 Jan 2025 16:46:25 +0100
> Mauro Carvalho Chehab wrote:
>
> > Adds a generic error device to handle generic hardware error
> > events as specified at ACPI 6.5 specification at 18.3.2.7.2:
> > https://uefi.org/specs/ACPI/6.5/
On Tue, Jan 28, 2025 at 06:42:02PM +0100, Mauro Carvalho Chehab wrote:
> Em Fri, 24 Jan 2025 13:30:54 +0100
> Igor Mammedov escreveu:
>
> > On Wed, 22 Jan 2025 16:46:25 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Adds a generic error device to handle generic hardware error
> > > events as
On 28/1/25 18:09, del...@kernel.org wrote:
From: Helge Deller
Since I contribute quite some code to hppa, I'd like to step up and
become the secondary maintainer for HPPA beside Richard.
Additionally change status of hppa machines to maintained as I will
take care of them.
Signed-off-by: Helge
Move the mips64el replay tests from tests/avocado/replay_kernel.py to
the functional framework. Since the functional tests should be run per
target, we cannot stick all replay tests in one file. Thus let's add
these tests to a separate file there now.
Signed-off-by: Thomas Huth
---
tests/avocado
Copy the ReplayKernelBase class from the avocado tests. We are going
to need it to convert the related replay tests in the following patches.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
tests/functional/replay_kernel.py | 84 +
Some tests have a very long runtime and might run into timeout issues
e.g. when QEMU has been compiled with --enable-debug. Add a decorator
for marking them more easily. Rename the corresponding environment
variable to be more in sync with the other QEMU_TEST_ALLOW_* switches
that we already have,
tests/avocado/replay_kernel.py is a rather big file with a lot of
Avocado-based tests in it. But in the long run, we rather want to
get away from Avocado, so we eventually have to convert these tests
to the functional framework. For this, we have to separate the tests
by target architecture, since
Move the mips big endian replay tests from tests/avocado/replay_kernel.py
to the functional framework. Since the functional tests should be run per
target, we cannot stick all replay tests in one file. Thus let's add
these tests to a separate file now.
Signed-off-by: Thomas Huth
---
tests/avocad
Move the mipsel replay tests from tests/avocado/replay_kernel.py to
the functional framework. Since the functional tests should be run per
target, we cannot stick all replay tests in one file. Thus let's add
these tests to a new, separate file there instead.
Signed-off-by: Thomas Huth
---
tests/
On Mon, 27 Jan 2025 at 14:48, Hongren Zheng wrote:
>
> On Mon, Jan 13, 2025 at 05:38:56PM +0800, Hongren Zheng wrote:
> > When USBPacket in OUT direction has larger payload
> > than the ep_out_buffer (of size 512), a buffer overflow
> > would occur.
> >
> > It could be fixed by limiting the size o
On Tue, 28 Jan 2025 at 19:20, Fabiano Rosas wrote:
> You could include qapi-types-migration.h and use the actual enum, that
> avoids the burden of having to keep the tests in sync with the code.
>
> (I don't think keeping the caps in sync with the current-version tests
> would break the compat tes
On 1/28/25 08:14, del...@kernel.org wrote:
From: Helge Deller
The hppa_hardware.h header file holds many constants for addresses and
offsets which are needed while building the firmware (SeaBIOS-hppa) and
while setting up the virtual machine in QEMU.
This patch brings it in sync between both so
On 1/28/25 08:14, del...@kernel.org wrote:
From: Helge Deller
The various PA-RISC CPUs implement different CPU-specific diag
instructions (mfdiag, mtdiag, mfcpu, mtcpu, ...) to access CPU-internal
diagnose/configuration registers, e.g. for cache control, managing space
register hashing, control
The test sequence boots from disk a mac99 machine in 64-bit mode, in
which case the CPU is a PPC 970.
The buildroot rootfs is built with config :
BR2_powerpc64=y
BR2_powerpc_970=y
and the kernel with the g5 deconfig.
Signed-off-by: Cédric Le Goater
---
MAINTAINERS |
Prasad Pandit writes:
> On Tue, 28 Jan 2025 at 11:00, Prasad Pandit wrote:
>> > for (int i = 0; i < MIGRATION_CAPABILITY__MAX; i++) {
>> > if (args->caps[i]) {
>> > migrate_set_capability(from,
>> > MigrationCapability_str(args->caps[i]), true);
>> > migrate_
We removed the old table-based decoder in favour of decodetree, but
we left a couple of typedefs that are now unused; delete them.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/targ
GICv3 isn't supported on aarch64/HVF, but GICv2 is.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: Test eventually timeouts :(
tests/qtest/migration/framework.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/migration/framework.c
b/tests/qtest/migration/fram
Allow tests to tune their parameters when running on HVF.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/migration/framework.h | 1 +
tests/qtest/migration/framework.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/tests/qtest/migration/framework.h
b/tests/qtest/migration/framewor
Previous commit removed the restriction on completing the full QDev
UNREALIZE step before removing vCPUs from global queue, it is now
safe to call cpu_list_remove() after accel_cpu_common_unrealize().
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 7 ++-
1 file changed, 2 insertion
cpu_list_add() was doing 2 distinct things:
- assign some index to vCPU
- add unrealized (thus in inconsistent state) vcpu to &cpus_queue
Code using CPU_FOREACH() macro would iterate over possibly
unrealized vCPUs, often dealt with special casing.
In order to avoid that, we move the addition of v
We are trying to understand what means "a qdev is realized".
One explanation was "the device is guest visible"; however
many devices are realized before being mapped, thus are not
"guest visible". Some devices map / wire their IRQs before
being realized (such ISA devices). There is a need for devic
Hi,
The goal of this series is to expose vCPUs in a stable state
to the accelerators, in particular the QDev 'REALIZED' step.
To do so we split the QTAILQ_INSERT/REMOVE calls from
cpu_list_add() / cpu_list_remove(), by moving them to the
DeviceClass::[un]wire() handlers, guaranty to be called jus
Invalidate TB with global vCPU queue locked.
See commit 4731f89b3b9 ("cpu: free cpu->tb_jmp_cache with RCU"):
Fixes the appended use-after-free. The root cause is that
during tb invalidation we use CPU_FOREACH, and therefore
to safely free a vCPU we must wait for an RCU grace period
Previous commits made sure vCPUs are realized before accelerators
(such KVM) use them. Ensure that by asserting the vCPU is created,
no need to return.
For more context, see commit 56adee407fc ("kvm: dirty-ring: Fix race
with vcpu creation").
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/
To call the hotplug handlers with REALIZED vCPU, we can
use the DeviceWire handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/cpu-common.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 9ee44a00277..8a02ac
Previous commit passed all our CI tests, this assertion being
never triggered. Remove it as dead code.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-all.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index cb56d120a91..814b1a53eb8
Philippe Mathieu-Daudé writes:
> &qemu_cpu_list_lock is locked within the WITH_QEMU_LOCK_GUARD()
> context, then unlocked. No need to manually unlock it.
>
> Fixes: 370ed600296 ("cpu: expose qemu_cpu_list_lock for lock-guard use")
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> migration/dirtyr
Philippe Mathieu-Daudé writes:
> Keep accelerator knowledge limited within MigrationTestEnv,
> expose a generic %has_dirty_ring value, only checking for
> KVM when initializing it in migration_get_env().
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Fabiano Rosas
This patch v2 has been successfully tested in s390x. Here the detailed
test steps:
Boot up a VM already containing a memory object
/home/qemu/build/qemu-system-s390x \
...
-m 4G,maxmem=20G \
-object memory-backend-ram,id=mem0,size=16G,reserve=off \
...
Check the virtio-balloon
(qemu) info balloon
On 28/1/25 13:41, BALATON Zoltan wrote:
On Tue, 28 Jan 2025, Harsh Prateek Bora wrote:
On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
Move the TCGCPUOps handlers to a new unit: tcg-excp_helper.c,
only built when TCG is selected.
Nice.
Just a thought - will the filename look better as excp_h
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/cpu-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index cb79566cc51..9ee44a00277 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -219,6 +219,14 @@ static void c
On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote:
>
> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
> serial. All other devices of the A53 memory map are represented as
> TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
> for running
On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote:
>
> While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus
> reference
> manual.
>
> Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
thanks
-- PMM
marcandre.lur...@redhat.com writes:
> From: Marc-André Lureau
>
> ../contrib/plugins/cache.c:638:9: error: ‘l2_cache’ may be used uninitialized
> [-Werror=maybe-uninitialized]
> 638 | append_stats_line(rep, l1_dmem_accesses, l1_dmisses,
> | ^~~
On 1/28/25 15:19, Stefan Hajnoczi wrote:
thread '' panicked at 'already borrowed',
rust/qemu-api/libqemu_api.rlib.p/structured/cell.rs:450:5
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
fatal runtime error: failed to initiate panic, error 5
https://gitlab.com/qem
From: Helge Deller
The 64-bit hppa qemu emulation still fails to boot 64-bit HP-UX.
This patch series improves the emulation a lot, since it enables us to boot
64-bit HP-UX installer silently up until an endless loop where the machine
reports that it's up an running (it crashed before). This stil
From: Helge Deller
The Diva GSP ("Guardian Service Processor") PCI boards are Remote
Management cards for PA-RISC machines. They come with built-in 16550A
UARTs for serial consoles and modem functionalities, as well as a
mailbox-like memory area for hardware auto-reboot functionality.
Latest ge
From: Helge Deller
PA-RISC CPUs have diagnose registers (%dr). Those are mostly
undocumented and control cache behaviour, memory behaviour, reset button
management and many other related internal CPU things.
The Linux kernel turns space-register hashing off unconditionally at
bootup. That code
From: Helge Deller
The hppa_hardware.h header file holds many constants for addresses and
offsets which are needed while building the firmware (SeaBIOS-hppa) and
while setting up the virtual machine in QEMU.
This patch brings it in sync between both source code repositories.
Signed-off-by: Helg
From: Helge Deller
Until now we used a standard serial-pci device to emulate a HP serial
console. This worked nicely with 32-bit Linux and 32-bit HP-UX, but
64-bit HP-UX crashes with it and expects either a Diva GSP card, or a real
64-bit capable PCI graphic card (which we don't have yet).
In or
Dear QEMU and KVM communities,
QEMU will apply for the Google Summer of Code internship
program again this year. Regular contributors can submit project
ideas that they'd like to mentor by replying to this email by
February 7th.
About Google Summer of Code
-
On 1/27/25 02:20, Jonathan Cameron wrote:
On Fri, 24 Jan 2025 12:55:52 -0800
Pierrick Bouvier wrote:
Hi Jonathan,
thanks for posting this. It's a creative usage of plugins.
I think that your current approach, decoupling plugins, CHMU and device
model is a good thing.
I'm not familiar with C
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
Previous commit removed the restriction on completing the full QDev
UNREALIZE step before removing vCPUs from global queue, it is now
safe to call cpu_list_remove() after accel_cpu_common_unrealize().
Signed-off-by: Philippe Mathieu-Daudé
---
cp
From: Bernhard Beschow
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of
each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share
the MSI IRQ with the INTx lines, so expose it as a dedicated pin.
Signed-off-by: Bernhard Beschow
Reviewed-by: Pe
From: Bernhard Beschow
The value of the UCFR register is respected when echoing characters to the
terminal, but its reset value is reserved. Fix the reset value to the one
documented in the datasheet.
While at it move the related attribute out of the section of unimplemented
registers since its
The advsimd_addh etc helpers defined in helper-a64.c are identical to
the vfp_addh etc helpers defined in helper-vfp.c: both take two
float16 inputs (in a uint32_t type) plus a float_status* and are
simple wrappers around the softfloat float16_* functions.
(The duplication seems to be a historical
Now we have moved all the uses of vfp.fp_status_f16 and FPST_FPCR_F16
to the new A32 or A64 fields, we can remove these.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250124162836.2332150-19-peter.mayd...@linaro.org
---
target/arm/cpu.h | 2 --
target/arm/t
In the A32 decoder, use FPST_A32 rather than FPST_FPCR. By
doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR(?!_)/FPST_A32/g' target/arm/tcg/translate-vfp.c
Si
On Tue, 28 Jan 2025 at 18:51, Richard Henderson
wrote:
>
> On 1/28/25 02:45, Peter Maydell wrote:
> > +static const TypeInfo omap_mmc_info = {
> > +.name = TYPE_OMAP_MMC,
> > +.parent = TYPE_SYS_BUS_DEVICE,
> > +.instance_size = sizeof(OMAPMMCState),
> > +.instance_init = omap_mmc_
Use the FPSR_ named constants in vfp_exceptbits_from_host(),
rather than hardcoded magic numbers.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250124162836.2332150-5-peter.mayd...@linaro.org
---
target/arm/vfp_helper.c | 12 ++--
1 file changed, 6 insertions
We directly use fp_status_f16 in a handful of helpers that
are AArch32-specific; switch to fp_status_f16_a32 for these.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250124162836.2332150-15-peter.mayd...@linaro.org
---
target/arm/tcg/vec_helper.c | 4 ++--
target/arm
From: Philippe Mathieu-Daudé
The ARMv7MState object is not simply a CPU, it also
contains the NVIC, SysTick timer, and various MemoryRegions.
Rename the field as 'armv7m', like other Cortex-M boards.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 2025011222561
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20250110160204.74997-3-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/stellaris.c b
From: Thomas Huth
We don't have any functional tests for this machine yet, thus let's
add a test with a MicroPython binary that is available online
(thanks to Joel Stanley for providing it, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg606064.html ).
Signed-off-by: Thomas Huth
Rev
Our float_flag_input_denormal exception flag is set when the fpu code
flushes an input denormal to zero. This is what many guest
architectures (eg classic Arm behaviour) require, but it is not the
only donarmal-related reason we might want to set an exception flag.
The x86 behaviour (which we do n
From: Philippe Mathieu-Daudé
Add definitions (DCx_periph) for the DeviceCapability bits,
replace direct bitmask checks with the DEV_CAP() macro,
which use the extract/deposit API.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20250110160204.74997-6-phi...@linaro.
On Tue, 28 Jan 2025, Cédric Le Goater wrote:
On 1/28/25 19:20, Thomas Huth wrote:
On 28/01/2025 19.07, Cédric Le Goater wrote:
The test sequence boots from disk a mac99 machine in 64-bit mode, in
which case the CPU is a PPC 970.
The buildroot rootfs is built with config :
BR2_powerpc64=y
BR2_
Now we have moved all the uses of vfp.fp_status and FPST_FPCR
to either the A32 or A64 fields, we can remove these.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250124162836.2332150-13-peter.mayd...@linaro.org
---
target/arm/cpu.h | 2 --
target/arm/tcg/tr
We want to split the existing fp_status in the Arm CPUState into
separate float_status fields for AArch32 and AArch64. (This is
because new control bits defined by FEAT_AFP only have an effect for
AArch64, not AArch32.) To make this split we will:
* define new fp_status_a32 and fp_status_a64 whic
In the A32 decoder, use FPST_A64_F16 rather than FPST_FPCR_F16.
By doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A64_F16/g'
target/arm/tcg/tra
In is_ebf(), we might be called for A64 or A32, but we have
the CPUARMState* so we can select fp_status_a64 or
fp_status_a32 accordingly.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Hongren Zheng
When USBPacket in OUT direction has larger payload
than the ep_out_buffer (of size 512), a buffer overflow
would occur.
It could be fixed by limiting the size of usb_packet_copy
to be at most buffer size. Further optimization gets rid
of the ep_out_buffer and directly uses ep
The helpers vfp_cmps, vfp_cmpes, vfp_cmpd, vfp_cmped are used only from
the A32 decoder; the A64 decoder uses separate vfp_cmps_a64 etc helpers
(because for A64 we update the main NZCV flags and for A32 we update
the FPSCR NZCV flags). So we can make these helpers use the fp_status_a32
field instea
From: Philippe Mathieu-Daudé
Add definitions for the number of controllers.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20250110160204.74997-5-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 25 +++--
1 file changed
From: Philippe Mathieu-Daudé
Board schematic is useful to corroborate GPIOs/IRQs wiring.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20250110160204.74997-2-phi...@linaro.org
[PMM: Use https:// URLs]
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 8
In vfp_exceptbits_from_host(), we accumulate the FPSR flags in
an "int", and our return type is also "int". However, the only
callsite returns the same information as a uint32_t, and
more generally we handle FPSR values in the code as uint32_t,
not int. Bring this function in to line with that conv
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
Invalidate TB with global vCPU queue locked.
See commit 4731f89b3b9 ("cpu: free cpu->tb_jmp_cache with RCU"):
Fixes the appended use-after-free. The root cause is that
during tb invalidation we use CPU_FOREACH, and therefore
to safe
In the A64 decoder, use FPST_A64 rather than FPST_FPCR. By
doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR(?!_)/FPST_A64/g'
target/arm/tcg/translate-{a64,sv
From: Philippe Mathieu-Daudé
There is nothing mapped at 0x40002000.
I2C#0 is already mapped at 0x40021000.
Remove the invalid mapping added in commits aecfbbc97a2 & 394c8bbfb7a.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20250110160204.74997-4-phi...@linaro.
From: Bernhard Beschow
Fixes characters to be "echoed" after each keystroke rather than after every
other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY
only after every other keystroke.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Peter Ma
From: Philippe Mathieu-Daudé
There are 2 I2C controllers, map them both, removing
the unimplemented one. Keep the OLED controller on the
first I2C bus.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20250110160204.74997-7-phi...@linaro.org
[PMM: tweak to appease m
From: Philippe Mathieu-Daudé
When instanciating the machine model, the machine_init()
implementations usually create the CPUs, so have access
to its first CPU. Use that rather then the &first_cpu
global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Samuel Ta
Our float_flag_output_denormal exception flag is set when
the fpu code flushes an output denormal to zero. Rename
it to float_flag_output_denormal_flushed:
* this keeps it parallel with the flag for flushing
input denormals, which we just renamed
* it makes it clearer that it doesn't mean "set
Switch from vfp.fp_status to vfp.fp_status_a64 for helpers which:
* directly reference an fp_status field
* are called only from the A64 decoder
* are not called inside a set_rmode/restore_rmode sequence
Signed-off-by: Peter Maydell
Message-id: 20250124162836.2332150-8-peter.mayd...@linaro.org
In the A32 decoder, use FPST_A32_F16 rather than FPST_FPCR_F16.
By doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A32_F16/g'
target/arm/tcg/tra
From: Philippe Mathieu-Daudé
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-off-by: Philippe Math
On Tue, 28 Jan 2025, Thomas Huth wrote:
On 28/01/2025 19.35, Cédric Le Goater wrote:
On 1/28/25 19:20, Thomas Huth wrote:
On 28/01/2025 19.07, Cédric Le Goater wrote:
The test sequence boots from disk a mac99 machine in 64-bit mode, in
which case the CPU is a PPC 970.
The buildroot rootfs is
As the first part of splitting the existing fp_status_f16
into separate float_status fields for AArch32 and AArch64
(so that we can make FEAT_AFP control bits apply only
for AArch64), define the two new fp_status_f16_a32 and
fp_status_f16_a64 fields, but don't use them yet.
Signed-off-by: Peter Ma
On Tue, 28 Jan 2025, Thomas Huth wrote:
On 28/01/2025 19.35, Cédric Le Goater wrote:
On 1/28/25 19:20, Thomas Huth wrote:
On 28/01/2025 19.07, Cédric Le Goater wrote:
The test sequence boots from disk a mac99 machine in 64-bit mode, in
which case the CPU is a PPC 970.
The buildroot rootfs
In softfloat-types.h a comment documents that if the float_status
field flush_to_zero is set then we flush denormalised results to 0
and set the inexact flag. This isn't correct: the status flag that
we set when flush_to_zero causes us to flush an output to zero is
float_flag_output_denormal_flush
On Tue, 28 Jan 2025, Thomas Huth wrote:
On 28/01/2025 19.35, Cédric Le Goater wrote:
On 1/28/25 19:20, Thomas Huth wrote:
On 28/01/2025 19.07, Cédric Le Goater wrote:
The test sequence boots from disk a mac99 machine in 64-bit mode, in
which case the CPU is a PPC 970.
The buildroot rootfs is
#x27; of
https://github.com/hdeller/qemu-hppa into staging (2025-01-24 14:43:07 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20250128-1
for you to fetch changes up to 664280abddcb3cacc9c6204706bb739fcc1316f7:
hw/u
Use fp_status_a32 in the vjcvt helper function; this is called only
from the A32/T32 decoder and is not used inside a
set_rmode/restore_rmode sequence.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250124162836.2332150-9-peter.mayd...@linaro.org
---
target/arm/vfp_he
We directly use fp_status_f16 in a handful of helpers that are
AArch64-specific; switch to fp_status_f16_a64 for these.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250124162836.2332150-16-peter.mayd...@linaro.org
---
target/arm/tcg/sme_helper.c | 4 ++--
target/arm
On 1/28/25 01:27, Daniel P. Berrangé wrote:
I'm not sure that's the case here.
32-on-32 is already effectively unmaintained, so we're not suffering
in terms of keeping the 32-on-32 code reliable.
Correct.
As evidence, on i686, the absolutely easiest available 32-bit host, we have the followin
We should be using the F16-specific float_status for conversions from
half-precision, because halfprec inputs never set Input Denormal.
Without FEAT_AHP, using the wrong fpst here had no effect, because
the only difference between the A64_F16 and A64 fpst is its handling
of flush-to-zero on input
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
We are trying to understand what means "a qdev is realized".
One explanation was "the device is guest visible"; however
many devices are realized before being mapped, thus are not
"guest visible". Some devices map / wire their IRQs before
being real
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/cpu-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index cb79566cc51..9ee44a00277 100644
--- a/hw/core/cpu-common.c
+++ b/hw/
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
cpu_list_add() was doing 2 distinct things:
- assign some index to vCPU
- add unrealized (thus in inconsistent state) vcpu to &cpus_queue
Code using CPU_FOREACH() macro would iterate over possibly
unrealized vCPUs, often dealt with special casing.
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
@@ -91,7 +91,6 @@ void cpu_list_add(CPUState *cpu)
} else {
assert(!cpu_index_auto_assigned);
}
-QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node);
cpu_list_generation_id++;
}
@@ -103,7 +102,6 @@ void cpu_list_remov
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
Previous commits made sure vCPUs are realized before accelerators
(such KVM) use them. Ensure that by asserting the vCPU is created,
no need to return.
For more context, see commit 56adee407fc ("kvm: dirty-ring: Fix race
with vcpu creation").
Sign
The pseudocode ResetSVEState() does:
FPSR = ZeroExtend(0x089f<31:0>, 64);
but QEMU's arm_reset_sve_state() called vfp_set_fpcr() by accident.
Before the advent of FEAT_AFP, this was only setting a collection of
RES0 bits, which vfp_set_fpsr() would then ignore, so the only effect
was that
On 1/28/25 06:21, Philippe Mathieu-Daudé wrote:
Previous commit passed all our CI tests, this assertion being
never triggered. Remove it as dead code.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-all.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/accel/kvm/kvm-all.c b
* Richard Henderson :
> On 1/28/25 17:52, Richard Henderson wrote:
> > On 1/28/25 14:45, del...@kernel.org wrote:
> > > + if (ctx->is_pa20 && (a->dr == 2)) {
> > > + /* Exit TB to recalculate gva_offset_mask on %dr2 */
> > > + ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
> > > + }
On 2025/01/28 20:18, Philippe Mathieu-Daudé wrote:
Since commit b14a0b7469f ("accel: Use QOM classes for accel types")
accelerators are registered as QOM objects. Use QOM as a generic
API to query for available accelerators. This is in particular
useful to query hardware accelerators such HFV, Xe
On 2025/01/28 23:48, Peter Maydell wrote:
On Sat, 4 Jan 2025 at 07:10, Akihiko Odaki wrote:
kvm-steal-time and sve properties are added for KVM even if the
corresponding features are not available. Always add pmu property for
Armv7+. Note that the property is added only for Armv7-A/R+ as QEMU
On 1/28/25 20:07, Helge Deller wrote:
What I'm not sure about is gva_offset_mask in those hunks and where you
said I can't read from env:
...
@@ -4635,6 +4641,7 @@ static void hppa_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->tb_flags = ctx->base.tb->flags;
ct
On 2025/01/28 22:54, Philippe Mathieu-Daudé wrote:
GICv3 isn't supported on aarch64/HVF, but GICv2 is.
Commit bdb0ade663c7 ("tests/migration-test: Stick with gicv3 in aarch64
test"), which set gic-version=3, says:
> Switch to a static gic version "3" rather than using version "max",
> so that
Em Tue, 28 Jan 2025 12:29:51 +0100
Mauro Carvalho Chehab escreveu:
> Em Fri, 24 Jan 2025 11:23:46 +0100
> Igor Mammedov escreveu:
>
> > On Wed, 22 Jan 2025 16:46:22 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Create a new property (x-has-hest-addr) and use it to detect if
> > > the GHE
On 28/01/2025 19.57, David Hildenbrand wrote:
Let's do it similar as virtio-balloon-pci. With this change, we can
use virtio-mem-pci on s390x, although plugging will still fail until
properly wired up in the machine.
No need to worry about transitional/non_transitional devices, because they
don'
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