We want to split the existing fp_status in the Arm CPUState into
separate float_status fields for AArch32 and AArch64. (This is
because new control bits defined by FEAT_AFP only have an effect for
AArch64, not AArch32.) To make this split we will:
* define new fp_status_a32 and fp_status_a64 which have
identical behaviour to the existing fp_status
* move existing uses of fp_status to fp_status_a32 or
fp_status_a64 as appropriate
* delete the old fp_status when it has no uses left
In this patch we add the new float_status fields.
We will also need to split fp_status_f16, but we will do that
as a separate series of patches.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250124162836.2332150-7-peter.mayd...@linaro.org
---
target/arm/cpu.h | 4 ++++
target/arm/tcg/translate.h | 12 ++++++++++++
target/arm/cpu.c | 2 ++
target/arm/vfp_helper.c | 12 ++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9a6e8e589cc..337c5383748 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -634,6 +634,8 @@ typedef struct CPUArchState {
/* There are a number of distinct float control structures:
*
* fp_status: is the "normal" fp status.
+ * fp_status_a32: is the "normal" fp status for AArch32 insns
+ * fp_status_a64: is the "normal" fp status for AArch64 insns
* fp_status_fp16: used for half-precision calculations
* standard_fp_status : the ARM "Standard FPSCR Value"
* standard_fp_status_fp16 : used for half-precision
@@ -659,6 +661,8 @@ typedef struct CPUArchState {
* an explicit FPSCR read.
*/
float_status fp_status;
+ float_status fp_status_a32;
+ float_status fp_status_a64;
float_status fp_status_f16;
float_status standard_fp_status;
float_status standard_fp_status_f16;
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 2d37d7c9f21..c8414d94d5e 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -671,6 +671,8 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const
TranslationBlock *tb)
*/
typedef enum ARMFPStatusFlavour {
FPST_FPCR,
+ FPST_A32,
+ FPST_A64,
FPST_FPCR_F16,
FPST_STD,
FPST_STD_F16,
@@ -686,6 +688,10 @@ typedef enum ARMFPStatusFlavour {
*
* FPST_FPCR
* for non-FP16 operations controlled by the FPCR
+ * FPST_A32
+ * for AArch32 non-FP16 operations controlled by the FPCR
+ * FPST_A64
+ * for AArch64 non-FP16 operations controlled by the FPCR
* FPST_FPCR_F16
* for operations controlled by the FPCR where FPCR.FZ16 is to be used
* FPST_STD
@@ -702,6 +708,12 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour
flavour)
case FPST_FPCR:
offset = offsetof(CPUARMState, vfp.fp_status);
break;
+ case FPST_A32:
+ offset = offsetof(CPUARMState, vfp.fp_status_a32);
+ break;
+ case FPST_A64:
+ offset = offsetof(CPUARMState, vfp.fp_status_a64);
+ break;
case FPST_FPCR_F16:
offset = offsetof(CPUARMState, vfp.fp_status_f16);
break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dc0231233a6..8bdd535db95 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -573,6 +573,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
set_default_nan_mode(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
arm_set_default_fp_behaviours(&env->vfp.fp_status);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index afc41420eb1..7475f97e0ce 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -64,6 +64,8 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
uint32_t i;
i = get_float_exception_flags(&env->vfp.fp_status);
+ i |= get_float_exception_flags(&env->vfp.fp_status_a32);
+ i |= get_float_exception_flags(&env->vfp.fp_status_a64);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
/* FZ16 does not generate an input denormal exception. */
i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
@@ -81,6 +83,8 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
* be the architecturally up-to-date exception flag information first.
*/
set_float_exception_flags(0, &env->vfp.fp_status);
+ set_float_exception_flags(0, &env->vfp.fp_status_a32);
+ set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
@@ -109,6 +113,8 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t
val, uint32_t mask)
break;
}
set_float_rounding_mode(i, &env->vfp.fp_status);
+ set_float_rounding_mode(i, &env->vfp.fp_status_a32);
+ set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
}
if (changed & FPCR_FZ16) {
@@ -122,10 +128,16 @@ static void vfp_set_fpcr_to_host(CPUARMState *env,
uint32_t val, uint32_t mask)
bool ftz_enabled = val & FPCR_FZ;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
}
if (changed & FPCR_DN) {
bool dnan_enabled = val & FPCR_DN;
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
}
}
--
2.34.1
