Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 8 ++--
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifive_u.c
The cells of 'initrd-start/end' should follow the '#address-cell'.
QEMU API could support 1 and 2 cells.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index ad45bd7a6a..76b099c696 1
Support to load DTB after 3GB on RV64 system, so that larger initrd
doesn't be overlapped to DTB. Update initrd DT to support different
"#address-cells".
Verify the patch via running 4GB initramfs on the virt machine.
Jim Shu (2):
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
On 10/18/24 16:13, Peter Maydell wrote:
List the olimex-stm32-h405 board in the document title, so that the
board name appears in the table of contents in system/target-arm.rst.
Signed-off-by: Peter Maydell
---
docs/system/arm/stm32.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(
On 10/18/24 16:13, Peter Maydell wrote:
The fby35 machine is not implemented in hw/arm/aspeed.c,
but its documentation is currently stuck at the end of aspeed.rst,
formatted in a way that it gets its own heading in the top-level
list of boards in target-arm.html.
We don't have any other boards t
On 18/10/24 07:17, Daniel P. Berrangé wrote:
The "special_features" field / parameter holds the subset of schema
features that are for internal code use. Specifically 'DEPRECATED'
and 'UNSTABLE'.
This special casing of internal features is going to be removed, so
prepare for that by renaming to
On 20/10/2024 23.37, Pierrick Bouvier wrote:
fix system target name, and remove --disable-system (which deactivates
system target).
Found using: make docker-test-build@debian-loongarch-cross V=1
Signed-off-by: Pierrick Bouvier
---
tests/docker/dockerfiles/debian-loongarch-cross.docker | 4 ++
On 20/10/24 18:37, Pierrick Bouvier wrote:
fix system target name, and remove --disable-system (which deactivates
system target).
Found using: make docker-test-build@debian-loongarch-cross V=1
Signed-off-by: Pierrick Bouvier
---
tests/docker/dockerfiles/debian-loongarch-cross.docker | 4 ++--
offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation
that was found on the Rust forums, and whose author agreed to license as
MIT for use in QEMU.
The alternative allows only one level of field access, but apart from this
can be used just by replacing core::mem::offset_of! wi
On 17/10/24 09:54, Ilya Leoshkevich wrote:
do_setcontext() copies the target sigmask without endianness handling
and then uses target_to_host_sigset_internal(), which expects a
byte-swapped one. Use target_to_host_sigset() instead.
These function names are confusing.
Fixes: bcd4933a23f1 ("lin
On 18/10/24 07:17, Daniel P. Berrangé wrote:
This updates the QAPI code generation to refer to 'features' instead
of 'special_features', in preparation for generalizing their exposure.
Signed-off-by: Daniel P. Berrangé
---
scripts/qapi/commands.py | 4 ++--
scripts/qapi/gen.py | 6 +++
On 10/18/24 16:13, Peter Maydell wrote:
Add a placeholder doc for the exynos4 boards nuri and smdkc210.
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
MAINTAINERS| 1 +
docs/system/arm/exynos.rst | 9 +
docs/system/target-arm.rst |
On 10/18/24 16:13, Peter Maydell wrote:
Add placeholder docs for the mcimx6ul-evk and mcimx7d-sabre boards.
Signed-off-by: Peter Maydell
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
MAINTAINERS | 2 ++
docs/system/arm/mcimx6ul-evk.rst | 5 +
docs/system/a
On 10/18/24 16:13, Peter Maydell wrote:
We now have at least placeholder documentation for every Arm board,
so we can remove the apologetic note that says that there are
undocumented ones which you can only find out about via the
``--machine help`` option.
Signed-off-by: Peter Maydell
---
doc
On 10/18/24 16:13, Peter Maydell wrote:
We have two Arm board doc files which both use '*-bmc' in their
documentation title. The result is that when you read the
table of contents in system/target-arm.html you don't know
which boards are covered by which file.
Expand out the board names entirely
On 11/10/2024 15.19, Thomas Huth wrote:
This patch series converts the tests/avocado/tuxrun_baselines.py
to the new functional test framework. While converting the sh4 test,
I noticed that the Avocado test was completely broken, so I included
a fix (revert) for that problem in this series, too.
On Tue, Oct 15, 2024 at 03:17:21PM +0200, Paolo Bonzini wrote:
> Date: Tue, 15 Oct 2024 15:17:21 +0200
> From: Paolo Bonzini
> Subject: [PATCH 03/16] rust: pass rustc_args when building all crates
> X-Mailer: git-send-email 2.46.2
>
> rustc_args is needed to smooth the difference in warnings betw
On 10/21/24 07:40, Junjie Mao wrote:
offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation
that was found on the Rust forums, and whose author agreed to license as
MIT for use in QEMU.
The alternative allows only one level of field access, but apart from this
can be used jus
On Thu, Oct 17, 2024 at 11:22 PM Thomas Huth wrote:
>
> On 10/09/2024 06.54, Alistair Francis wrote:
> > This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
> >
> > This converts the RISC-V charecter device callers of qemu_chr_fe_write()
> > to either use qemu_chr_fe_write_all()
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741)
* mn
+Zhiyi
On 10/20/24 15:01, Avihai Horon wrote:
vfio_state_pending_exact() is used to update migration core how much
device data is left for the device migration. Currently, the sum of
pre-copy and stop-copy sizes of the VFIO device are reported.
The pre-copy size is obtained via the VFIO_MIG_GET
On 10/21/24 03:49, Guenter Roeck wrote:
Hi,
On Sat, Jun 08, 2024 at 10:40:58AM +0200, Paolo Bonzini wrote:
This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish
the job.
Signed-off-by: Paolo Bonzini
Reviewed-by: Richard Henderson
While testing qemu v9.1, I noticed the fol
On Fri, 18 Oct 2024 at 12:35, Naresh Kamboju wrote:
>
> The QEMU-ARMv7 boot has failed with the Linux next-20241017 tag.
> The boot log is incomplete, and no kernel crash was detected.
> However, the system did not proceed far enough to reach the login prompt.
>
> Please find the incomplete boot l
Hi Salil,
On 10/14/24 16:22, Salil Mehta wrote:
Reflect the ACPI CPU hotplug `is_{present, enabled}` states in the `_STA.PRES`
(presence) and `_STA.ENA` (enabled) bits when the guest kernel evaluates the
ACPI `_STA` method during initialization, as well as when vCPUs are hot-plugged
or hot-unplu
Hi Igor,
On 10/18/24 11:46, Igor Mammedov wrote:
On Mon, 14 Oct 2024 20:22:01 +0100
Salil Mehta wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after the kernel has booted. This is because many system
initializations depend on the exact CPU cou
On Sat, Oct 19, 2024 at 12:15 AM Peter Maydell wrote:
>
> Add a placeholder doc for the xlnx-zcu102 board.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistair
> ---
> MAINTAINERS | 1 +
> docs/system/arm/xlnx-zcu102.rst | 19 +++
> doc
On Sat, Oct 19, 2024 at 12:14 AM Peter Maydell wrote:
>
> We now have at least placeholder documentation for every Arm board,
> so we can remove the apologetic note that says that there are
> undocumented ones which you can only find out about via the
> ``--machine help`` option.
>
> Signed-off-by
From: Richard Henderson
Assert that op is known and that cc_op_live_ is populated.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 1 -
target/i386/tcg/translate.c | 21 ++---
target/i386/tcg/decode-new.c.inc | 2 +-
target/i386/tcg/emit.c.inc |
From: Richard Henderson
Make const. Use the read-only strings directly; do not copy
them into an on-stack buffer with snprintf. Allow for holes
in the cc_op_str array, now present with CC_OP_POPCNT.
Fixes: 460231ad369 ("target/i386: give CC_OP_POPCNT low bits corresponding to
MO_TL")
Signed-o
This includes improved translation of checks, microoptimization of the
helpers, and improvements to the cc_op_* functions from Richard.
Unlike his original patches[1] I didn't convert cc_op_live() to a switch
statement, instead keeping the array but making sure that all of its
entries are nonzero.
Most uses of CC_OP_DYNAMIC are for CMP/JB/JE or similar sequences.
We can optimize many of them to avoid computation of the flags.
This eliminates both TCG ops to set up the new cc_op, and helper
instructions because evaluating just ZF is much cheaper.
Signed-off-by: Paolo Bonzini
---
target/i38
This gives greater opportunity for reassociation on x86 targets,
since addition can use the LEA instruction.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/i386/tcg/cc
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 6e89d4faef1..5d729e68c98 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1193,6 +1193
This removes the 256 byte parity table from the executable on
x86, s390 and RISC-V/zbb hosts.
Signed-off-by: Paolo Bonzini
---
include/qemu/host-utils.h| 16
target/i386/tcg/helper-tcg.h | 12
target/i386/tcg/cc_helper_template.h.inc | 20
If the operands of the arithmetic instruction fit within a half-register,
it's easiest to use a comparison instruction to compute the carry.
`
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 37
1 file changed, 37 insertions(+)
diff --git a/ta
From: Richard Henderson
Give the first few enumerators explicit integer constants,
align the BWLQ enumerators.
This will be used to simplify ((op - CC_OP_*B) & 3).
Signed-off-by: Richard Henderson
Link:
https://lore.kernel.org/r/20240701025115.1265117-4-richard.hender...@linaro.org
Signed-off
Mostly used for TEST+JG and TEST+JLE, but it is easy to cover
also JBE/JA and JL/JGE; shaves about 0.5% TCG ops.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/
From: Richard Henderson
Replace arithmetic on cc_op with a helper function.
Assert that the op has a size and that it is valid
for the configuration.
Signed-off-by: Richard Henderson
Link:
https://lore.kernel.org/r/20240701025115.1265117-6-richard.hender...@linaro.org
Signed-off-by: Paolo Bonz
Just use CC_OP_EFLAGS; it is not that likely that the flags computed by
CC_OP_CLR survive the end of the basic block, in which case there is no
need to spill cc_op_src.
cc_op_src now does need spilling if the XOR is followed by a memory
operation, but this only costs 0.2% extra TCG ops. They will
This makes it easier for the compiler to understand the bits that are set,
and removes "cltq" instructions to canonicalize the output value as 32-bit
signed.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 46
1 file changed, 23 insertions(+),
Prefer it to gen_ext_tl in the common case where the destination is known.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index ef190416b49
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d3bbcf7317c..6e89d4faef1 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -993,6 +993,7
On 10/18/24 08:33, Akihiko Odaki wrote:
>> diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
>> index 0d1de7dc398c..cfd4ed8a104f 100644
>> --- a/hw/display/virtio-gpu.c
>> +++ b/hw/display/virtio-gpu.c
>> @@ -1521,6 +1521,21 @@ void virtio_gpu_device_realize(DeviceState
>> *qdev, Error
On Thu, Oct 17, 2024 at 5:35 AM Richard Henderson
wrote:
>
> The first immediate field is unsigned, whereas operand_vimm
> extracts a signed value. There is no need to mask the result
> with 'u'; just print the immediate with 'i'.
>
> Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for
On Fri, Oct 18, 2024 at 12:55 AM Clément Léger wrote:
>
> Add the switch to enable the Smdbltrp ISA extension.
>
> Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/ta
On Thu, Oct 17, 2024 at 5:33 AM Richard Henderson
wrote:
>
> Introduce support for the RISC-V vector extension in the TCG backend.
>
> v5:
> https://lore.kernel.org/qemu-devel/20241007025700.47259-1-zhiwei_...@linux.alibaba.com/
>
> Changes for v6:
> - Fix problem with TB overflow restart wrt t
On Thu, Oct 17, 2024 at 5:35 AM Richard Henderson
wrote:
>
> From: TANG Tiancheng
>
> Add support for probing RISC-V vector extension availability in
> the backend. This information will be used when deciding whether
> to use vector instructions in code generation.
>
> Cache lg2(vlenb) for the ba
Hi,
On Sat, Jun 08, 2024 at 10:40:58AM +0200, Paolo Bonzini wrote:
> This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish
> the job.
>
> Signed-off-by: Paolo Bonzini
> Reviewed-by: Richard Henderson
While testing qemu v9.1, I noticed the following crash when testing
qemu-sy
On Fri, Oct 18, 2024 at 12:54 AM Clément Léger wrote:
>
> When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
> while SSTATUS.SDT isn't cleared, generate a double trap exception to
> M-mode.
>
> Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Alistair
> ---
> t
On 10/18/24 08:22, Akihiko Odaki wrote:
...
>> + EGLDisplay egl_display;
>> +
>> + if (!x_disp) {
>> + return;
>> + }
>> +
>> + /* Prefer EGL over GLX to get dma-buf support. */
>> + egl_display = eglGetDisplay((EGLNativeDisplayType)x_disp);
>> +> + if (egl_display != EGL_N
On Fri, Oct 18, 2024 at 12:54 AM Clément Léger wrote:
>
> Add the switch to enable the Ssdbltrp ISA extension.
>
> Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/ta
On Fri, Oct 18, 2024 at 12:55 AM Clément Léger wrote:
>
> With the current implementation, if we had the current scenario:
> - set bit x in menvcfg
> - set bit x in henvcfg
> - clear bit x in menvcfg
> then, the internal variable env->henvcfg would still contain bit x due
> to both a wrong menvcfg
On Fri, Oct 18, 2024 at 12:53 AM Clément Léger wrote:
>
> When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
> when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
> when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning
> to VU from HS.
>
> Si
On Fri, Oct 18, 2024 at 12:54 AM Clément Léger wrote:
>
> Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior.
> Also set MDT to 1 at reset according to the specification.
>
> Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c
On Fri, Oct 18, 2024 at 12:54 AM Clément Léger wrote:
>
> When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
> when executing sret if executed in M-mode. When executing mret/mnret,
> SSTATUS.MDT is cleared.
>
> Signed-off-by: Clément Léger
> ---
> target/riscv/op_helper.c | 12
On Fri, Oct 18, 2024 at 12:54 AM Clément Léger wrote:
>
> When the Smsdbltrp ISA extension is enabled, if a trap happens while
> MSTATUS.MDT is already set, it will trigger an abort or an NMI is the
> Smrnmi extension is available.
>
> Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
On Thu, Oct 17, 2024 at 5:35 AM Richard Henderson
wrote:
>
> This pointer needs to be reset after overflow just like
> code_buf and code_ptr.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 57a269469db ("tcg: Infrastructure for managing constant pools")
> Signed-off-by: Richard Henderson
Acked-by: Alist
Hi,
On Fri, Jul 19, 2024 at 11:07:01AM +1000, Richard Henderson wrote:
> We can determine at translation time whether the insn is or
> is not dbczl. We must retain a runtime check against the
> HID5 register, but we can move that to a separate function
> that never affects other ppc models.
>
>
On 10/17/24 05:54, Ilya Leoshkevich wrote:
do_setcontext() copies the target sigmask without endianness handling
and then uses target_to_host_sigset_internal(), which expects a
byte-swapped one. Use target_to_host_sigset() instead.
Fixes: bcd4933a23f1 ("linux-user: ppc signal handling")
Signed-o
fix system target name, and remove --disable-system (which deactivates
system target).
Found using: make docker-test-build@debian-loongarch-cross V=1
Signed-off-by: Pierrick Bouvier
---
tests/docker/dockerfiles/debian-loongarch-cross.docker | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
Peter Maydell writes:
> In target-arm.rst there is an apologetic note:
>
> Unfortunately many of the Arm boards QEMU supports are currently
> undocumented; you can get a complete list by running
> ``qemu-system-aarch64 --machine help``.
>
> However, the situation isn't actually as bleak as
On 10/20/24 08:53, Paolo Bonzini wrote:
This removes the 256 byte parity table from the executable on
x86, s390 and RISC-V/zbb hosts.
Signed-off-by: Paolo Bonzini
---
include/qemu/host-utils.h| 16
target/i386/tcg/helper-tcg.h | 12
On 10/20/24 08:53, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
Reviewed-by: Richard Henderson
r~
Hi Aleksandar,
On 18/10/24 10:19, Aleksandar Rakic wrote:
Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().
Cherry-picked 4cc974938aee1588f852590509004e340c072940
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Yongbok Kim
Si
On 10/20/24 10:39, Naresh Kamboju wrote:
On Fri, 18 Oct 2024 at 12:35, Naresh Kamboju wrote:
The QEMU-ARMv7 boot has failed with the Linux next-20241017 tag.
The boot log is incomplete, and no kernel crash was detected.
However, the system did not proceed far enough to reach the login prompt.
在 2024/10/19 0:31, Kevin Wolf 写道:
Am 22.08.2024 um 12:52 hat luzhipeng geschrieben:
issue:https://gitlab.com/qemu-project/qemu/-/issues/1357
empty vmdk only contains metadata, ovftool failed.
So it allocates more one sector for empty disk. the ovftool
command line: ovftool input.ovf output.ov
Julian Ganz writes:
> Some analysis greatly benefits, or depends on, information about
> interrupts. For example, we may need to handle the execution of a new
> translation block differently if it is not the result of normal program
> flow but of an interrupt.
For future iterations please post a
On 10/20/24 08:53, Paolo Bonzini wrote:
Prefer it to gen_ext_tl in the common case where the destination is known.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson
r~
Data sizes in VFIO migration trace events are printed in hex format
while in migration core trace events they are printed in decimal format.
This inconsistency makes it less readable when using both trace event
types. Hence, change the data sizes print format to decimal in VFIO
migration trace eve
vfio_state_pending_exact() is used to update migration core how much
device data is left for the device migration. Currently, the sum of
pre-copy and stop-copy sizes of the VFIO device are reported.
The pre-copy size is obtained via the VFIO_MIG_GET_PRECOPY_INFO ioctl,
which returns the amount of
When the VM is shut down vfio_vmstate_change/_prepare() are called to
transition the VFIO device state to STOP. They are called after
migration_shutdown() and thus, by this time, the migration object is
already freed (more specifically, MigrationState->qemu_file_lock is
already destroyed).
In this
This small series contains some bug fixes and cleanups.
Reviews are welcome.
Thanks.
Avihai Horon (3):
vfio/migration: Report only stop-copy size in
vfio_state_pending_exact()
vfio/migration: Refactor vfio_vmstate_change/_prepare() error
reporting
vfio/migration: Change trace format
On 10/18/24 15:20, Aleksandar Rakic wrote:
This patch reverts the commit (with SHA
50290c002c045280f8defad911901e16bfb52884 from
https://github.com/MIPS/gnutools-qemu) that breaks for mingw builds,
where clock_gettime and CLOCK_MONOTONIC are not available.
Cherry-picked d57c735e1af1ca719dbd0c3a9
On 10/20/24 08:53, Paolo Bonzini wrote:
From: Richard Henderson
Assert that op is known and that cc_op_live_ is populated.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 1 -
target/i386/tcg/translate.c | 21 ++---
target/i386/tcg/decode-new.c.in
On 10/20/24 08:53, Paolo Bonzini wrote:
Just use CC_OP_EFLAGS; it is not that likely that the flags computed by
CC_OP_CLR survive the end of the basic block, in which case there is no
need to spill cc_op_src.
cc_op_src now does need spilling if the XOR is followed by a memory
operation, but this
On 10/20/24 08:53, Paolo Bonzini wrote:
Most uses of CC_OP_DYNAMIC are for CMP/JB/JE or similar sequences.
We can optimize many of them to avoid computation of the flags.
This eliminates both TCG ops to set up the new cc_op, and helper
instructions because evaluating just ZF is much cheaper.
Sig
On 10/20/24 08:53, Paolo Bonzini wrote:
Mostly used for TEST+JG and TEST+JLE, but it is easy to cover
also JBE/JA and JL/JGE; shaves about 0.5% TCG ops.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 22 ++
1 file changed, 22 insertions(+)
Reviewed-by: Ri
On 10/20/24 08:53, Paolo Bonzini wrote:
This makes it easier for the compiler to understand the bits that are set,
and removes "cltq" instructions to canonicalize the output value as 32-bit
signed.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 46 -
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3195da512..fed64741d1 100644
--- a/target/riscv/cpu.
From: Tommy Wu
Because the RNMI interrupt trap handler address is implementation defined.
We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
of the harts. It’s very easy for users to set the address based on their
expectation. This patch also adds the functionality to
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 11 ++
target/r
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
83 matches
Mail list logo