This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +++
target/loongarch/helper.h | 17 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +++
target/loongarch/insns.decode
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34 +++
target/loongarch/helper.h | 12 +
target/loongarch/insn_trans/trans_lsx.c.inc | 75 ++
target/loongarch/insns
This patch includes:
- VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +++
target/loongarch/helper.h | 17 +++
target/loongarch/insn_trans/trans
This patch includes:
- VFCVT{L/H}.{S.H/D.S};
- VFCVT.{H.S/S.D};
- VFRINT[{RNE/RZ/RP/RM}].{S/D};
- VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- VFTINT[RZ].{WU.S/LU.D};
- VFTINT[{RNE/RZ/RP/RM}].W.D;
- VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- VFFINT.{S.W/D.L}[U];
- VFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off-by: Song G
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++
3 files changed, 15 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 18 +++
target/loongarch/helper.h | 18 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 18 +++
target/loongarch/insns.decode
This patch includes:
- VILV{L/H}.{B/H/W/D};
- VSHUF.{B/H/W/D};
- VSHUF4I.{B/H/W/D};
- VPERMI.W;
- VEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 25 +++
target/loongarch/helper.h | 25 +++
target/loongarch/insn_trans/trans_lsx.c.
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43
target/loongarch/helper.h | 43
target/loongarc
This patch includes:
- VSSRLRN.{B.H/H.W/W.D};
- VSSRARN.{B.H/H.W/W.D};
- VSSRLRN.{BU.H/HU.W/WU.D};
- VSSRARN.{BU.H/HU.W/WU.D};
- VSSRLRNI.{B.H/H.W/W.D/D.Q};
- VSSRARNI.{B.H/H.W/W.D/D.Q};
- VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loonga
This patch includes:
- VLDI.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 7 +
target/loongarch/helper.h | 2 +
target/loongarch/insn_trans/trans_lsx.c.inc | 10 ++
target/loongarch/insns.decode | 4 +
target/loongarch/lsx_helpe
This patch includes:
- VFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 ++
target/loongarch/insns.decode | 5 ++
target/loongarch
This patch includes:
- VSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5
target/loongarch/helper.h | 5
target/loongarch/insn_trans/trans_lsx.c.inc | 5
target/loongarch/insns.decode | 5
targe
This patch includes:
- VABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 +++
target/loongarch/helper.h | 9 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 +++
target/loongarch/insns.decode | 9 +++
target/lo
This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 +++
target/loongarch/insn_trans/trans_l
This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 25 +++
target/loongarch/helper.h | 25 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 25 +++
target/loo
Hi, Merry Christmas!
This series adds LoongArch LSX instructions, Since the LoongArch
Vol2 is not open, So we use 'RFC' title.
About Test:
The new-abi gcc which support LSX is also not open, We use the old-abi gcc [1]
build
test code[2](tests/tcg/loongarch/vec/test_XXX*.c).
[1]:http://ftp.lo
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++
target/loongarch/insns.decode | 5 +++
target/loong
This patch includes:
- VFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 94 +
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 30 +++
target/loongarch/insns.decode
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 7 +++
target/loongarch/helper.h | 7 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 7 +++
target/loongarch/insns.decode
This patch includes:
- VMADD.{B/H/W/D};
- VMSUB.{B/H/W/D};
- VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34
target/loongarch/helper.h | 34
target/loong
This patch includes:
- VBITSEL.V;
- VBITSELI.B;
- VSET{EQZ/NEZ}.V;
- VSETANYEQZ.{B/H/W/D};
- VSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 20
target/loongarch/helper.h | 14 +++
target/loongarch/insn_trans/trans_lsx.c.in
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9
target/loongarch/helper.h | 9
target/loongarch/insn_trans/trans_lsx.c.inc | 9
target/loongarch/ins
This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9
target/loongarch/helper.h | 9
target/loongarch/insn_trans/trans_lsx.c.inc | 9
target/loongarch/insns.decode |
This patch includes:
- VREPLVE[I].{B/H/W/D};
- VBSLL.V, VBSRL.V;
- VPACK{EV/OD}.{B/H/W/D};
- VPICK{EV/OD}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 35 +++
target/loongarch/helper.h | 30 +++
target/loongarch/insn_trans/trans_lsx.c.i
This patch includes:
- VSSRLN.{B.H/H.W/W.D};
- VSSRAN.{B.H/H.W/W.D};
- VSSRLN.{BU.H/HU.W/WU.D};
- VSSRAN.{BU.H/HU.W/WU.D};
- VSSRLNI.{B.H/H.W/W.D/D.Q};
- VSSRANI.{B.H/H.W/W.D/D.Q};
- VSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disa
This patch includes:
- VMUL.{B/H/W/D};
- VMUH.{B/H/W/D}[U];
- VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 38
target/loongarch/helper.h | 38
target/loonga
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 59ae29a3b4..698778ce7f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -385,6 +385,7 @@ static void loongarch_la464_init
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +
target/loongarch/lsx_helper.c | 6 ++
target/loongarch/meson.build| 1 +
target/loongarch/translate.c| 1 +
4 files changed, 13 insertions(+)
create mode 100644 ta
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 33 +
target/loongarch/helper.h | 18 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 53 +++
ta
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 46 +
target/loongarch/fp
This patch includes:
- VADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5
target/loongarch/helper.h | 5
target/loongarch/insn_trans/trans_lsx.c.inc | 5
target/loongarch/insns.decode | 5
target/l
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 23 ++
target/loongarch/helper.h | 12 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 23 ++
target/loongarch/insns.decode
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +++
target/loongarch/helper.h | 17 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +++
target/loongarch/insns.decode
This patch includes:
- VSEQ[I].{B/H/W/D};
- VSLE[I].{B/H/W/D}[U];
- VSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43 +++
target/loongarch/helper.h | 43 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 43 +++
target/loong
This patch includes:
- VMAX[I].{B/H/W/D}[U];
- VMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 33 +++
target/loongarch/helper.h | 34 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 33 +++
target/loongarch/insns.decode
This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 12
target/loongarch/helper.h | 12
target/loongarch/insn_trans/trans_lsx.c.inc | 12
target/loongarch/insns.dec
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 +++
target/loongarch/helper.h | 9 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 +++
tar
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 4 ++--
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu.h | 18 +-
target/loongarch/gdbstub.c | 4 ++--
target/loongarch/machine.c | 2 +-
5 files changed, 23 insertions(+), 7 deletio
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 36
target/loongarch/helper.h | 36
target/loongarch/insn_trans/trans_lsx.c.inc | 36
This patch includes:
- VSRLRN.{B.H/H.W/W.D};
- VSRARN.{B.H/H.W/W.D};
- VSRLRNI.{B.H/H.W/W.D/D.Q};
- VSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 +++
target/loongarch/insn_trans/tra
This patch includes:
- VSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 +++
target/loongarch/helper.h | 9 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 +++
target/loongarch/insns.decode | 12
target/lo
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +++
target/loongarch/helper.h | 17 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +++
target/loongarch/insns.decode
This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 14 +
target/loongarch/helper.h | 9 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 21 +++
target/loongarch/insns.decode
This patch includes;
- VNEG.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 10 +
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 16
target/loongarch/insns.decode | 7
targe
On 23/12/22 21:43, Vladimir Sementsov-Ogievskiy wrote:
Make prototypes correspond to their origins. Also drop
address_space_rw_cached() which doesn't exist anywhere in the code.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/coverity-scan/model.c | 15 +--
1 file changed
On Fri, Dec 23, 2022 at 06:27:07AM +0100, Markus Armbruster wrote:
> "Michael S. Tsirkin" writes:
>
> > On Thu, Dec 22, 2022 at 11:48:25AM +0100, Markus Armbruster wrote:
> >> Bernhard Beschow writes:
> >>
> >> > Am 22. Dezember 2022 10:03:23 UTC schrieb Markus Armbruster
> >> > :
> >> >>Back
From: Longpeng
The generic vhost-vdpa device and the commit a585fad26b ("vdpa: request
iova_range only once") are merged in the same pull request, and the later
would cause the generic vhost-vdpa device work improperly.
Patch 1 fixes the problem and patch 2 hardens the error path of vdpa/net.
L
From: Longpeng
We should stop if the GET_IOVA_RANGE ioctl failed.
Signed-off-by: Longpeng
---
net/vhost-vdpa.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index ffdc435d19..e65023d013 100644
--- a/net/vhost-vdpa.c
+++ b/net/vho
From: Longpeng
In commit a585fad26b ("vdpa: request iova_range only once") we remove
GET_IOVA_RANGE form vhost_vdpa_init, the generic vdpa device will start
without iova_range populated, so the device won't work. Let's call
GET_IOVA_RANGE ioctl explicitly.
Fixes: a585fad26b2e6ccc ("vdpa: request
On 12/23/22 06:32, Ilya Leoshkevich wrote:
+mmap_lock();
+p = pageflags_find(address, address);
+mmap_unlock();
How does the code ensure that p is not freed here?
+return p ? p->flags : 0;
Yep, need to use g_free_rcu.
+while (true) {
+PageFlagsNode *p = pagefla
On 12/23/22 04:02, Ilya Leoshkevich wrote:
+static void *thread_write(void *arg)
+{
+struct context *ctx = arg;
+struct timespec *ts;
+size_t i, j;
+int ret;
+
+for (i = 0; ctx->mutator_count; i++) {
+j = (i & PAGE_IDX_MASK) | PAGE_IDX_W_MASK;
+/* Write directl
From: Ilya Leoshkevich
Add a test that locklessly changes and exercises page protection bits
from various threads. This helps catch race conditions in the VMA
handling.
Signed-off-by: Ilya Leoshkevich
Message-Id: <20221223120252.513319-1-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
When called from syscall(), we are not within a TB and pc == 0.
We can skip the check for invalidating the current TB.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-maint.c | 78
1 file changed, 43 insertions(+), 35 deletions(-)
diff --git a/acce
As in page_get_flags, we need to try again with the mmap
lock held if we fail a page lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 39 ---
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/u
Fix all three bugs pointed out by Ilya, and for the moment at least,
adjust the testcase to set read+write for writability.
r~
Ilya Leoshkevich (1):
tests/tcg/multiarch: add vma-pthread.c
Richard Henderson (3):
accel/tcg: Fix tb_invalidate_phys_page_unwind
accel/tcg: Use g_free_rcu for u
Because we allow lockless lookups, we have to be careful
when it is freed. Use rcu to delay the free until safe.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/u
On 12/24/22 00:15, Song Gao wrote:
Hi, Merry Christmas!
This series adds LoongArch LSX instructions, Since the LoongArch
Vol2 is not open, So we use 'RFC' title.
That is unfortunate, as it makes reviewing this difficult.
Is there a timeline for this being published?
In the meantime, I can at
On 12/24/22 00:15, Song Gao wrote:
+#define LSX_LEN (128)
+typedef union vec_t vec_t;
+union vec_t {
+int8_t B[LSX_LEN / 8];
+int16_t H[LSX_LEN / 16];
+int32_t W[LSX_LEN / 32];
+int64_t D[LSX_LEN / 64];
+__int128 Q[LSX_LEN / 128];
+};
+
+typedef union fpr_t fpr_t;
+unio
On 12/24/22 00:15, Song Gao wrote:
+static bool gen_vvv(DisasContext *ctx, arg_vvv *a,
+void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+TCGv_i32 vd = tcg_constant_i32(a->vd);
+TCGv_i32 vj = tcg_constant_i32(a->vj);
+TCGv_i32 vk = tcg_constant_i32(a->vk);
On 12/24/22 00:15, Song Gao wrote:
+union fpr_t {
+uint64_t d;
+vec_t vec;
+};
+
struct LoongArchTLB {
uint64_t tlb_misc;
/* Fields corresponding to CSR_TLBELO0/1 */
@@ -251,7 +267,7 @@ typedef struct CPUArchState {
uint64_t gpr[32];
uint64_t pc;
-uint64_t
On 12/24/22 00:15, Song Gao wrote:
+static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+TCGv_i32 vd = tcg_constant_i32(a->vd);
+TCGv_i32 vj = tcg_constant_i32(a->vj);
+TCGv_i32 imm = tcg_constant_i32(a->i
On 12/24/22 00:15, Song Gao wrote:
+TRANS(vneg_b, gen_vv, gen_helper_vneg_b)
+TRANS(vneg_h, gen_vv, gen_helper_vneg_h)
+TRANS(vneg_w, gen_vv, gen_helper_vneg_w)
+TRANS(vneg_d, gen_vv, gen_helper_vneg_d)
These can be implemented with tcg_gen_gvec_neg.
r~
On 12/24/22 00:15, Song Gao wrote:
+TRANS(vsadd_b, gen_vvv, gen_helper_vsadd_b)
+TRANS(vsadd_h, gen_vvv, gen_helper_vsadd_h)
+TRANS(vsadd_w, gen_vvv, gen_helper_vsadd_w)
+TRANS(vsadd_d, gen_vvv, gen_helper_vsadd_d)
+TRANS(vsadd_bu, gen_vvv, gen_helper_vsadd_bu)
+TRANS(vsadd_hu, gen_vvv, gen_helpe
On 12/24/22 00:15, Song Gao wrote:
+union vec_t {
+int8_t B[LSX_LEN / 8];
+int16_t H[LSX_LEN / 16];
+int32_t W[LSX_LEN / 32];
+int64_t D[LSX_LEN / 64];
+__int128 Q[LSX_LEN / 128];
Oh, you can't use __int128 directly.
It won't compile on 32-bit hosts.
r~
On 12/24/22 00:15, Song Gao wrote:
+#define S_EVEN(a, bit) \
+int64_t)(a)) << (64 - bit / 2)) >> (64 - bit / 2))
+
+#define U_EVEN(a, bit) \
+uint64_t)(a)) << (64 - bit / 2)) >> (64 - bit / 2))
+
+#define S_ODD(a, bit) \
+int64_t)(a)) << (64 - bit)) >> (64 - bi
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vaddwev_h_b, gen_vvv, gen_helper_vaddwev_h_b)
+TRANS(vaddwev_w_h, gen_vvv, gen_helper_vaddwev_w_h)
+TRANS(vaddwev_d_w, gen_vvv, gen_helper_vaddwev_d_w)
+TRANS(vaddwev_q_d, gen_vvv, gen_helper_vaddwev_q_d)
+TRANS(vaddwod_h_b, gen_vvv, gen_helper_vaddwod_h_
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vavg_b, gen_vvv, gen_helper_vavg_b)
+TRANS(vavg_h, gen_vvv, gen_helper_vavg_h)
+TRANS(vavg_w, gen_vvv, gen_helper_vavg_w)
+TRANS(vavg_d, gen_vvv, gen_helper_vavg_d)
+TRANS(vavg_bu, gen_vvv, gen_helper_vavg_bu)
+TRANS(vavg_hu, gen_vvv, gen_helper_vavg_hu)
On 12/24/22 00:16, Song Gao wrote:
+INSN_LSX(vabsd_b, vvv)
+INSN_LSX(vabsd_h, vvv)
+INSN_LSX(vabsd_w, vvv)
+INSN_LSX(vabsd_d, vvv)
+INSN_LSX(vabsd_bu, vvv)
+INSN_LSX(vabsd_hu, vvv)
+INSN_LSX(vabsd_wu, vvv)
+INSN_LSX(vabsd_du, vvv
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vadda_b, gen_vvv, gen_helper_vadda_b)
+TRANS(vadda_h, gen_vvv, gen_helper_vadda_h)
+TRANS(vadda_w, gen_vvv, gen_helper_vadda_w)
+TRANS(vadda_d, gen_vvv, gen_helper_vadda_d)
These can be implemented with abs + add.
r~
On 12/24/22 00:16, Song Gao wrote:
+INSN_LSX(vmax_b, vvv)
+INSN_LSX(vmax_h, vvv)
+INSN_LSX(vmax_w, vvv)
+INSN_LSX(vmax_d, vvv)
+INSN_LSX(vmin_b, vvv)
+INSN_LSX(vmin_h, vvv)
+INSN_LSX(vmin_w, vvv)
+INSN_LSX(vmin_d, vvv
On 12/24/22 00:16, Song Gao wrote:
+DEF_HELPER_4(vmul_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vmul_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vmul_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vmul_d, void, env, i32, i32, i32)
These are tcg_gen_gvec_mul.
+DEF_HELPER_4(vmuh_b, void, env, i32,
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vmadd_b, gen_vvv, gen_helper_vmadd_b)
+TRANS(vmadd_h, gen_vvv, gen_helper_vmadd_h)
+TRANS(vmadd_w, gen_vvv, gen_helper_vmadd_w)
+TRANS(vmadd_d, gen_vvv, gen_helper_vmadd_d)
+TRANS(vmsub_b, gen_vvv, gen_helper_vmsub_b)
+TRANS(vmsub_h, gen_vvv, gen_helper_v
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vsat_b, gen_vv_i, gen_helper_vsat_b)
+TRANS(vsat_h, gen_vv_i, gen_helper_vsat_h)
+TRANS(vsat_w, gen_vv_i, gen_helper_vsat_w)
+TRANS(vsat_d, gen_vv_i, gen_helper_vsat_d)
+TRANS(vsat_bu, gen_vv_i, gen_helper_vsat_bu)
+TRANS(vsat_hu, gen_vv_i, gen_helper_vsa
On 12/24/22 00:16, Song Gao wrote:
+static void do_vsigncov(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+switch (bit) {
+case 8:
+Vd->B[n] = (Vj->B[n] == 0x0) ? 0 :
+ (Vj->B[n] < 0) ? -Vk->B[n] : Vk->B[n];
+break;
+case 16:
+Vd->H[n] =
On 12/24/22 00:16, Song Gao wrote:
+static void do_vmskltz(vec_t *Vd, vec_t *Vj, int bit, int n)
+{
+switch (bit) {
+case 8:
+Vd->H[0] |= ((0x80 & Vj->B[n]) == 0) << n;
+break;
+case 16:
+Vd->H[0] |= ((0x8000 & Vj->H[n]) == 0) << n;
+break;
+case 32
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vand_v, gen_vvv, gen_helper_vand_v)
+TRANS(vor_v, gen_vvv, gen_helper_vor_v)
+TRANS(vxor_v, gen_vvv, gen_helper_vxor_v)
+TRANS(vnor_v, gen_vvv, gen_helper_vnor_v)
+TRANS(vandn_v, gen_vvv, gen_helper_vandn_v)
+TRANS(vorn_v, gen_vvv, gen_helper_vorn_v)
Th
On 12/24/22 00:16, Song Gao wrote:
+DEF_HELPER_4(vsll_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vsll_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vsll_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vsll_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vslli_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vslli_h
On 12/24/22 00:16, Song Gao wrote:
+DEF_HELPER_4(vseq_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vseq_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vseq_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vseq_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vseqi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vseqi_h
On 12/24/22 00:16, Song Gao wrote:
+DEF_HELPER_5(vbitsel_v, void, env, i32, i32, i32, i32)
This is tcg_gen_gvec_bitsel. The immediate version would require dupi.
r~
On 12/24/22 00:16, Song Gao wrote:
+DEF_HELPER_4(vinsgr2vr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vinsgr2vr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vinsgr2vr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vinsgr2vr_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_b, void, env, i32, i32, i
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vreplve_b, gen_vvr, gen_helper_vreplve_b)
+TRANS(vreplve_h, gen_vvr, gen_helper_vreplve_h)
+TRANS(vreplve_w, gen_vvr, gen_helper_vreplve_w)
+TRANS(vreplve_d, gen_vvr, gen_helper_vreplve_d)
+TRANS(vreplvei_b, gen_vv_i, gen_helper_vreplvei_b)
+TRANS(vreplve
On 12/24/22 00:16, Song Gao wrote:
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34 +++
target/loongarch/helper.h | 12 +
target/loongarch/insn_trans/trans_lsx.c.i
On 12/24/22 00:16, Song Gao wrote:
+static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
+{
+TCGv_i32 twd = tcg_constant_i32(a->vd);
+TCGv_i32 tui = tcg_constant_i32(a->imm);
+
+CHECK_SXE;
+gen_helper_vldi(cpu_env, twd, tui);
+return true;
+}
+
The constant should be expan
On 12/22/22 13:55, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (6):
hw/arm/aspeed: Fix smpboot[] on big-endian hosts
hw/arm/raspi: Fix smpboot[] on big-endian hosts
hw/arm/exynos4210: Remove tswap32() calls and constify smpboot[]
hw/arm/npcm7xx: Remove tswap32() calls and con
On 12/23/22 01:01, Alexander Graf wrote:
The finalize_gic_version() function tries to determine which GIC version
the current accelerator / host combination supports. During the initial
HVF porting efforts, I didn't realize that I also had to touch this
function. Then Zenghui brought up this func
Like CONFIG_TCG, the enabled method of execution is a host property
not a guest property. This exposes the define to compile-once files.
Acked-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
1 file changed, 1 insertion(+), 3 del
We now check the consistency of reg_to_temp[] with each update,
so the utility of checking consistency at the end of each
opcode is minimal. In addition, the form of this check is
quite expensive, consuming 10% of a checking-enabled build.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderso
Create two new functions, set_temp_val_{reg,nonreg}.
Assert that the reg_to_temp mapping is correct before
any changes are made.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 159 +-
1 file changed, 85 insertions(+)
For v5, I've not omitted some of the reviewed patches, as I did for v4.
There are only a couple of patches lacking review:
15-tcg-Fix-tcg_reg_alloc_dup.patch
19-tcg-Introduce-paired-register-allocation.patch
36-tcg-Vary-the-allocation-size-for-TCGOp.patch
38-tcg-Reorg-function-calls.patch
Remove whitespace at end of line, plus one place this also
highlights some missing braces.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 33 +
tcg/ppc/tcg-target.c.inc | 2 +-
2 files changed, 18 insertions(+
Use the official extend/extract functions instead of routines
that will shortly be internal to tcg.
Cc: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 21 -
1 file changed, 4 insertions(+), 17 deletions(-
Change 32-bit tci TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EVEN, to
force 32-bit values to be aligned to 64-bit. With a small reorg
to the argument processing loop, this neatly replaces an ifdef for
CONFIG_TCG_INTERPRETER.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Create a wrapper for locking/unlocking the iothread lock.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/main-loop.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h
inde
Pre-compute the function call layout for each helper at startup.
Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps
in the op->args[] array. This allows several places to stop
checking for NULL TCGTemp, to which TCG_CALL_DUMMY_ARG mapped.
For tcg_gen_callN, loop over the arguments once.
The hppa host code has been removed since 2013; this
should have been deleted at the same time.
Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/tcg
Narrow the scope of the lock to the actual read/write,
moving the cpu_transation_failed call outside the lock.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git
From: Philippe Mathieu-Daudé
We are going to modify this code, so fix its style first to avoid:
ERROR: spaces required around that '*' (ctx:VxV)
#281: FILE: tcg/s390x/tcg-target.c.inc:1224:
+uintptr_t mask = ~(0xull << i*16);
^
Revie
The assignment to mem_coherent should be done with any
modification, not simply with a newly allocated register.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 05d2b70ab7..371908b34b 100644
--- a/
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 278d163803..241d06bab8 10064
Add a helper function for computing the size of a type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 16
tcg/tcg.c | 27 ---
2 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/include/
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