This patch includes;
- VNEG.{B/H/W/D}.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 10 +++++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 16 ++++++++
target/loongarch/insns.decode | 7 ++++
target/loongarch/lsx_helper.c | 42 +++++++++++++++++++++
5 files changed, 80 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 13a503951a..53e299b4ba 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -773,6 +773,11 @@ static void output_vv_i(DisasContext *ctx, arg_vv_i *a,
const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
}
+static void output_vv(DisasContext *ctx, arg_vv *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "v%d, v%d", a->vd, a->vj);
+}
+
INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv)
@@ -792,3 +797,8 @@ INSN_LSX(vsubi_bu, vv_i)
INSN_LSX(vsubi_hu, vv_i)
INSN_LSX(vsubi_wu, vv_i)
INSN_LSX(vsubi_du, vv_i)
+
+INSN_LSX(vneg_b, vv)
+INSN_LSX(vneg_h, vv)
+INSN_LSX(vneg_w, vv)
+INSN_LSX(vneg_d, vv)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index d6d50f6771..847950011e 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -151,3 +151,8 @@ DEF_HELPER_4(vsubi_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vsubi_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vsubi_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vsubi_du, void, env, i32, i32, i32)
+
+DEF_HELPER_3(vneg_b, void, env, i32, i32)
+DEF_HELPER_3(vneg_h, void, env, i32, i32)
+DEF_HELPER_3(vneg_w, void, env, i32, i32)
+DEF_HELPER_3(vneg_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 9485a03a08..00514709c1 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -39,6 +39,17 @@ static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a,
return true;
}
+static bool gen_vv(DisasContext *ctx, arg_vv *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 vd = tcg_constant_i32(a->vd);
+ TCGv_i32 vj = tcg_constant_i32(a->vj);
+
+ CHECK_SXE;
+ func(cpu_env, vd, vj);
+ return true;
+}
+
TRANS(vadd_b, gen_vvv, gen_helper_vadd_b)
TRANS(vadd_h, gen_vvv, gen_helper_vadd_h)
TRANS(vadd_w, gen_vvv, gen_helper_vadd_w)
@@ -58,3 +69,8 @@ TRANS(vsubi_bu, gen_vv_i, gen_helper_vsubi_bu)
TRANS(vsubi_hu, gen_vv_i, gen_helper_vsubi_hu)
TRANS(vsubi_wu, gen_vv_i, gen_helper_vsubi_wu)
TRANS(vsubi_du, gen_vv_i, gen_helper_vsubi_du)
+
+TRANS(vneg_b, gen_vv, gen_helper_vneg_b)
+TRANS(vneg_h, gen_vv, gen_helper_vneg_h)
+TRANS(vneg_w, gen_vv, gen_helper_vneg_w)
+TRANS(vneg_d, gen_vv, gen_helper_vneg_d)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 4f8226060a..3da5ed17ed 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -489,12 +489,14 @@ dbcl 0000 00000010 10101 ...............
@i15
# LSX Argument sets
#
+&vv vd vj
&vvv vd vj vk
&vv_i vd vj imm
#
# LSX Formats
#
+@vv .... ........ ..... ..... vj:5 vd:5 &vv
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
@@ -517,3 +519,8 @@ vsubi_bu 0111 00101000 11000 ..... ..... .....
@vv_ui5
vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5
vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5
vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5
+
+vneg_b 0111 00101001 11000 01100 ..... ..... @vv
+vneg_h 0111 00101001 11000 01101 ..... ..... @vv
+vneg_w 0111 00101001 11000 01110 ..... ..... @vv
+vneg_d 0111 00101001 11000 01111 ..... ..... @vv
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index e227db20d3..0fd17bf08f 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -20,6 +20,10 @@
uint32_t vd, uint32_t vj, uint32_t imm) \
{ FUNC(env, vd, vj, imm, BIT, __VA_ARGS__ ); }
+#define DO_HELPER_VV(NAME, BIT, FUNC, ...) \
+ void helper_##NAME(CPULoongArchState *env, uint32_t vd, uint32_t vj) \
+ { FUNC(env, vd, vj, BIT, __VA_ARGS__); }
+
static void helper_vvv(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t vk, int bit,
void (*func)(vec_t*, vec_t*, vec_t*, int, int))
@@ -47,6 +51,19 @@ static void helper_vv_i(CPULoongArchState *env,
}
}
+static void helper_vv(CPULoongArchState *env,
+ uint32_t vd, uint32_t vj, int bit,
+ void (*func)(vec_t*, vec_t*, int, int))
+{
+ int i;
+ vec_t *Vd = &(env->fpr[vd].vec);
+ vec_t *Vj = &(env->fpr[vj].vec);
+
+ for (i = 0; i < LSX_LEN/bit; i++) {
+ func(Vd, Vj, bit, i);
+ }
+}
+
static void do_vadd(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
{
switch (bit) {
@@ -152,3 +169,28 @@ DO_HELPER_VV_I(vsubi_bu, 8, helper_vv_i, do_vsubi)
DO_HELPER_VV_I(vsubi_hu, 16, helper_vv_i, do_vsubi)
DO_HELPER_VV_I(vsubi_wu, 32, helper_vv_i, do_vsubi)
DO_HELPER_VV_I(vsubi_du, 64, helper_vv_i, do_vsubi)
+
+static void do_vneg(vec_t *Vd, vec_t *Vj, int bit, int n)
+{
+ switch (bit) {
+ case 8:
+ Vd->B[n] = -Vj->B[n];
+ break;
+ case 16:
+ Vd->H[n] = -Vj->H[n];
+ break;
+ case 32:
+ Vd->W[n] = -Vj->W[n];
+ break;
+ case 64:
+ Vd->D[n] = -Vj->D[n];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_VV(vneg_b, 8, helper_vv, do_vneg)
+DO_HELPER_VV(vneg_h, 16, helper_vv, do_vneg)
+DO_HELPER_VV(vneg_w, 32, helper_vv, do_vneg)
+DO_HELPER_VV(vneg_d, 64, helper_vv, do_vneg)
--
2.31.1
