This patch includes:
- VSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 5 ++++
target/loongarch/helper.h | 5 ++++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 ++++
target/loongarch/insns.decode | 5 ++++
target/loongarch/lsx_helper.c | 29 +++++++++++++++++++++
5 files changed, 49 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 3187f87bbe..34a459410b 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1050,3 +1050,8 @@ INSN_LSX(vexth_hu_bu, vv)
INSN_LSX(vexth_wu_hu, vv)
INSN_LSX(vexth_du_wu, vv)
INSN_LSX(vexth_qu_du, vv)
+
+INSN_LSX(vsigncov_b, vvv)
+INSN_LSX(vsigncov_h, vvv)
+INSN_LSX(vsigncov_w, vvv)
+INSN_LSX(vsigncov_d, vvv)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 7a9d4f125d..c2b4407663 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -405,3 +405,8 @@ DEF_HELPER_3(vexth_hu_bu, void, env, i32, i32)
DEF_HELPER_3(vexth_wu_hu, void, env, i32, i32)
DEF_HELPER_3(vexth_du_wu, void, env, i32, i32)
DEF_HELPER_3(vexth_qu_du, void, env, i32, i32)
+
+DEF_HELPER_4(vsigncov_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vsigncov_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vsigncov_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vsigncov_d, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 48ea07b645..ce207eda05 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -321,3 +321,8 @@ TRANS(vexth_hu_bu, gen_vv, gen_helper_vexth_hu_bu)
TRANS(vexth_wu_hu, gen_vv, gen_helper_vexth_wu_hu)
TRANS(vexth_du_wu, gen_vv, gen_helper_vexth_du_wu)
TRANS(vexth_qu_du, gen_vv, gen_helper_vexth_qu_du)
+
+TRANS(vsigncov_b, gen_vvv, gen_helper_vsigncov_b)
+TRANS(vsigncov_h, gen_vvv, gen_helper_vsigncov_h)
+TRANS(vsigncov_w, gen_vvv, gen_helper_vsigncov_w)
+TRANS(vsigncov_d, gen_vvv, gen_helper_vsigncov_d)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 8ae9ca608e..c7237730d3 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -777,3 +777,8 @@ vexth_hu_bu 0111 00101001 11101 11100 ..... .....
@vv
vexth_wu_hu 0111 00101001 11101 11101 ..... ..... @vv
vexth_du_wu 0111 00101001 11101 11110 ..... ..... @vv
vexth_qu_du 0111 00101001 11101 11111 ..... ..... @vv
+
+vsigncov_b 0111 00010010 11100 ..... ..... ..... @vvv
+vsigncov_h 0111 00010010 11101 ..... ..... ..... @vvv
+vsigncov_w 0111 00010010 11110 ..... ..... ..... @vvv
+vsigncov_d 0111 00010010 11111 ..... ..... ..... @vvv
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index a094d7d382..73360e45e2 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -1829,3 +1829,32 @@ DO_HELPER_VV(vexth_hu_bu, 16, helper_vv, do_vexth_u)
DO_HELPER_VV(vexth_wu_hu, 32, helper_vv, do_vexth_u)
DO_HELPER_VV(vexth_du_wu, 64, helper_vv, do_vexth_u)
DO_HELPER_VV(vexth_qu_du, 128, helper_vv, do_vexth_u)
+
+static void do_vsigncov(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ switch (bit) {
+ case 8:
+ Vd->B[n] = (Vj->B[n] == 0x0) ? 0 :
+ (Vj->B[n] < 0) ? -Vk->B[n] : Vk->B[n];
+ break;
+ case 16:
+ Vd->H[n] = (Vj->H[n] == 0x0) ? 0 :
+ (Vj->H[n] < 0) ? -Vk->H[n] : Vk->H[n];
+ break;
+ case 32:
+ Vd->W[n] = (Vj->W[n] == 0x0) ? 0 :
+ (Vj->W[n] < 0) ? -Vk->W[n] : Vk->W[n];
+ break;
+ case 64:
+ Vd->D[n] = (Vj->D[n] == 0x0) ? 0 :
+ (Vj->D[n] < 0) ? -Vk->D[n] : Vk->W[n];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_VVV(vsigncov_b, 8, helper_vvv, do_vsigncov)
+DO_HELPER_VVV(vsigncov_h, 16, helper_vvv, do_vsigncov)
+DO_HELPER_VVV(vsigncov_w, 32, helper_vvv, do_vsigncov)
+DO_HELPER_VVV(vsigncov_d, 64, helper_vvv, do_vsigncov)
--
2.31.1
