This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 12 ++++
target/loongarch/helper.h | 12 ++++
target/loongarch/insn_trans/trans_lsx.c.inc | 12 ++++
target/loongarch/insns.decode | 13 +++++
target/loongarch/lsx_helper.c | 62 +++++++++++++++++++++
5 files changed, 111 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index b674167120..3e8015ac0e 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1062,3 +1062,15 @@ INSN_LSX(vmskltz_w, vv)
INSN_LSX(vmskltz_d, vv)
INSN_LSX(vmskgez_b, vv)
INSN_LSX(vmsknz_b, vv)
+
+INSN_LSX(vand_v, vvv)
+INSN_LSX(vor_v, vvv)
+INSN_LSX(vxor_v, vvv)
+INSN_LSX(vnor_v, vvv)
+INSN_LSX(vandn_v, vvv)
+INSN_LSX(vorn_v, vvv)
+
+INSN_LSX(vandi_b, vv_i)
+INSN_LSX(vori_b, vv_i)
+INSN_LSX(vxori_b, vv_i)
+INSN_LSX(vnori_b, vv_i)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index ae9351f513..77b576f22f 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -417,3 +417,15 @@ DEF_HELPER_3(vmskltz_w, void, env, i32, i32)
DEF_HELPER_3(vmskltz_d, void, env, i32, i32)
DEF_HELPER_3(vmskgez_b, void, env, i32, i32)
DEF_HELPER_3(vmsknz_b, void, env, i32,i32)
+
+DEF_HELPER_4(vand_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vxor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vnor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vandn_v, void, env, i32, i32, i32)
+DEF_HELPER_4(vorn_v, void, env, i32, i32, i32)
+
+DEF_HELPER_4(vandi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vxori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vnori_b, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index c02602c409..c12de1d3d4 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -333,3 +333,15 @@ TRANS(vmskltz_w, gen_vv, gen_helper_vmskltz_w)
TRANS(vmskltz_d, gen_vv, gen_helper_vmskltz_d)
TRANS(vmskgez_b, gen_vv, gen_helper_vmskgez_b)
TRANS(vmsknz_b, gen_vv, gen_helper_vmsknz_b)
+
+TRANS(vand_v, gen_vvv, gen_helper_vand_v)
+TRANS(vor_v, gen_vvv, gen_helper_vor_v)
+TRANS(vxor_v, gen_vvv, gen_helper_vxor_v)
+TRANS(vnor_v, gen_vvv, gen_helper_vnor_v)
+TRANS(vandn_v, gen_vvv, gen_helper_vandn_v)
+TRANS(vorn_v, gen_vvv, gen_helper_vorn_v)
+
+TRANS(vandi_b, gen_vv_i, gen_helper_vandi_b)
+TRANS(vori_b, gen_vv_i, gen_helper_vori_b)
+TRANS(vxori_b, gen_vv_i, gen_helper_vxori_b)
+TRANS(vnori_b, gen_vv_i, gen_helper_vnori_b)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 864a524fe6..03b7f76712 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -502,6 +502,7 @@ dbcl 0000 00000010 10101 ...............
@i15
@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
@vv_ui6 .... ........ .... imm:6 vj:5 vd:5 &vv_i
+@vv_ui8 .... ........ .. imm:8 vj:5 vd:5 &vv_i
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
@@ -789,3 +790,15 @@ vmskltz_w 0111 00101001 11000 10010 ..... .....
@vv
vmskltz_d 0111 00101001 11000 10011 ..... ..... @vv
vmskgez_b 0111 00101001 11000 10100 ..... ..... @vv
vmsknz_b 0111 00101001 11000 11000 ..... ..... @vv
+
+vand_v 0111 00010010 01100 ..... ..... ..... @vvv
+vor_v 0111 00010010 01101 ..... ..... ..... @vvv
+vxor_v 0111 00010010 01110 ..... ..... ..... @vvv
+vnor_v 0111 00010010 01111 ..... ..... ..... @vvv
+vandn_v 0111 00010010 10000 ..... ..... ..... @vvv
+vorn_v 0111 00010010 10001 ..... ..... ..... @vvv
+
+vandi_b 0111 00111101 00 ........ ..... ..... @vv_ui8
+vori_b 0111 00111101 01 ........ ..... ..... @vv_ui8
+vxori_b 0111 00111101 10 ........ ..... ..... @vv_ui8
+vnori_b 0111 00111101 11 ........ ..... ..... @vv_ui8
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index cea1d99eb6..c61479bf74 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -1912,3 +1912,65 @@ DO_HELPER_VV(vmskltz_w, 32, helper_vv_z, do_vmskltz)
DO_HELPER_VV(vmskltz_d, 64, helper_vv_z, do_vmskltz)
DO_HELPER_VV(vmskgez_b, 8, helper_vv_z, do_vmskgez)
DO_HELPER_VV(vmsknz_b, 8, helper_vv_z, do_vmsknz)
+
+static void do_vand_v(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ Vd->D[n] = Vj->D[n] & Vk->D[n];
+}
+
+static void do_vor_v(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ Vd->D[n] = Vj->D[n] | Vk->D[n];
+}
+
+static void do_vxor_v(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ Vd->D[n] = Vj->D[n] ^ Vk->D[n];
+}
+
+static void do_vnor_v(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ Vd->D[n] = ~(Vj->D[n] | Vk->D[n]);
+}
+
+static void do_vandn_v(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ Vd->D[n] = ~Vj->D[n] & Vk->D[n];
+}
+
+static void do_vorn_v(vec_t *Vd, vec_t *Vj, vec_t *Vk, int bit, int n)
+{
+ Vd->D[n] = Vj->D[n] | ~Vk->D[n];
+}
+
+DO_HELPER_VVV(vand_v, 64, helper_vvv, do_vand_v)
+DO_HELPER_VVV(vor_v, 64, helper_vvv, do_vor_v)
+DO_HELPER_VVV(vxor_v, 64, helper_vvv, do_vxor_v)
+DO_HELPER_VVV(vnor_v, 64, helper_vvv, do_vnor_v)
+DO_HELPER_VVV(vandn_v, 64, helper_vvv, do_vandn_v)
+DO_HELPER_VVV(vorn_v, 64, helper_vvv, do_vorn_v)
+
+static void do_vandi_b(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+ Vd->B[n] = Vj->B[n] & imm;
+}
+
+static void do_vori_b(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+ Vd->B[n] = Vj->B[n] | imm;
+}
+
+static void do_vxori_b(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+ Vd->B[n] = Vj->B[n] ^ imm;
+}
+
+static void do_vnori_b(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+ Vd->B[n] = ~(Vj->B[n] | imm);
+}
+
+DO_HELPER_VV_I(vandi_b, 8, helper_vv_i, do_vandi_b)
+DO_HELPER_VV_I(vori_b, 8, helper_vv_i, do_vori_b)
+DO_HELPER_VV_I(vxori_b, 8, helper_vv_i, do_vxori_b)
+DO_HELPER_VV_I(vnori_b, 8, helper_vv_i, do_vnori_b)
--
2.31.1
